bcm53xx: add first 5.17 DTS changes
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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From 58d3d07985c1adab31a3ed76360d016bb1c5b358 Mon Sep 17 00:00:00 2001
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From: Matthew Hagan <mnhagan88@gmail.com>
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Date: Fri, 15 Oct 2021 23:50:22 +0100
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Subject: [PATCH] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties
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This patch enables two properties for the QCA8337 switches on the MX65.
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Set the SGMII transmit clock to falling edge
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"qca,sgmii-txclk-falling-edge" to conform to the OEM configuration [1].
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The new explicit PLL enable option "qca,sgmii-enable-pll" is required
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[2].
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[1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be
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[2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6
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Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
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+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi
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@@ -118,6 +118,8 @@
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reg = <0>;
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ethernet = <&sgmii1>;
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phy-mode = "sgmii";
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+ qca,sgmii-enable-pll;
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+ qca,sgmii-txclk-falling-edge;
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fixed-link {
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speed = <1000>;
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full-duplex;
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@@ -194,6 +196,8 @@
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reg = <0>;
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ethernet = <&sgmii0>;
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phy-mode = "sgmii";
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+ qca,sgmii-enable-pll;
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+ qca,sgmii-txclk-falling-edge;
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fixed-link {
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speed = <1000>;
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full-duplex;
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@ -0,0 +1,29 @@
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From 835992e7eca4b29a87c204cefff2f7863fd087f3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Wed, 27 Oct 2021 00:57:03 +0800
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Subject: [PATCH] ARM: dts: BCM5301X: remove unnecessary address & size cells
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from Asus RT-AC88U
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Remove the unnecessary #address-cells & #size-cells in the gpio-keys node
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from the device tree of Asus RT-AC88U.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 --
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1 file changed, 2 deletions(-)
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--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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@@ -68,8 +68,6 @@
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gpio-keys {
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compatible = "gpio-keys";
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- #address-cells = <1>;
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- #size-cells = <0>;
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wps {
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label = "WPS";
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@ -0,0 +1,104 @@
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From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Wed, 27 Oct 2021 00:57:06 +0800
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Subject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Define the Realtek RTL8365MB switch without interrupt support on the device
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tree of Asus RT-AC88U.
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Acked-by: Alvin Šipraga <alsi@bang-olufsen.dk>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++
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1 file changed, 77 insertions(+)
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--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
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@@ -93,6 +93,83 @@
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gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
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};
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};
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+
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+ switch {
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+ compatible = "realtek,rtl8365mb";
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+ /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */
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+ mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
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+ mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
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+ reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
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+ realtek,disable-leds;
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+ dsa,member = <1 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan5";
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+ phy-handle = <ðphy0>;
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan6";
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+ phy-handle = <ðphy1>;
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan7";
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+ phy-handle = <ðphy2>;
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan8";
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+ phy-handle = <ðphy3>;
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&sw0_p5>;
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+ phy-mode = "rgmii";
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+ tx-internal-delay-ps = <2000>;
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+ rx-internal-delay-ps = <2000>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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+
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+ mdio {
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+ compatible = "realtek,smi-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethphy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+
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+ ethphy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+
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+ ethphy2: ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+
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+ ethphy3: ethernet-phy@3 {
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+ reg = <3>;
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+ };
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+ };
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+ };
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};
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&srab {
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@ -14,11 +14,9 @@ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
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index f92089290ccd..ec5de636796e 100644
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -408,7 +408,7 @@ uart2: serial@18008000 {
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@@ -408,7 +408,7 @@
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i2c0: i2c@18009000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x18009000 0x50>;
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@ -27,6 +25,3 @@ index f92089290ccd..ec5de636796e 100644
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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--
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2.25.1
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@ -51,7 +51,7 @@ Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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};
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&uart0 {
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@@ -196,3 +168,31 @@
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@@ -229,3 +195,31 @@
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};
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};
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};
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