mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-15 11:24:42 +00:00
remove 2.6.27 patches
SVN-Revision: 16894
This commit is contained in:
Florian Fainelli
parent
8050025e9d
commit
1ccffe43f2
@ -1,11 +0,0 @@
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--- a/arch/mips/au1000/mtx-1/init.c
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+++ b/arch/mips/au1000/mtx-1/init.c
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@@ -49,7 +49,7 @@ void __init prom_init(void)
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prom_argv = (char **)fw_arg1;
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prom_envp = (char **)fw_arg2;
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- prom_init_cmdline();
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+ strcpy(arcs_cmdline, CONFIG_CMDLINE);
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memsize_str = prom_getenv("memsize");
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if (!memsize_str)
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@ -1,11 +0,0 @@
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--- a/arch/mips/au1000/mtx-1/platform.c
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+++ b/arch/mips/au1000/mtx-1/platform.c
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@@ -90,7 +90,7 @@ static struct platform_device mtx1_gpio_
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static struct mtd_partition mtx1_mtd_partitions[] = {
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{
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- .name = "filesystem",
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+ .name = "rootfs",
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.size = 0x01C00000,
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.offset = 0,
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},
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@ -1,15 +0,0 @@
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--- a/drivers/net/au1000_eth.c
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+++ b/drivers/net/au1000_eth.c
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@@ -1293,9 +1293,12 @@ static void set_rx_mode(struct net_devic
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}
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}
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+#define AU1000_KNOWN_PHY_IOCTLS (SIOCGMIIPHY & 0xfff0)
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static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
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{
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struct au1000_private *aup = (struct au1000_private *)dev->priv;
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+ if((cmd & AU1000_KNOWN_PHY_IOCTLS) != AU1000_KNOWN_PHY_IOCTLS)
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+ return -EINVAL;
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if (!netif_running(dev)) return -EINVAL;
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@ -1,31 +0,0 @@
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--- a/drivers/net/au1000_eth.c
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+++ b/drivers/net/au1000_eth.c
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@@ -184,6 +184,15 @@ struct au1000_private *au_macs[NUM_ETH_I
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# undef AU1XXX_PHY1_IRQ
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#endif
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+#if defined(CONFIG_MIPS_MTX1)
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+/*
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+ * 4G MeshCube (MTX-1) board
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+ * PHY is at address 31 on MAC0
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+ * autodetect fails if not searched for highest address !
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+ */
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+# define AU1XXX_PHY_SEARCH_HIGHEST_ADDR
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+#endif
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+
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#if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0)
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# error MAC0-associated PHY attached 2nd MACs MII bus not supported yet
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#endif
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@@ -380,6 +389,12 @@ static int mii_probe (struct net_device
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aup->old_duplex = -1;
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aup->phy_dev = phydev;
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+#ifdef CONFIG_MIPS_MTX1
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+ /* set up ethernet jack LEDs on the 4G MeshCube (MTX-1 board) */
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+ printk(KERN_INFO "MTX-1 PHY: updating LED settings\n");
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+ phy_write(phydev, 0x11, 0xff80);
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+#endif
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+
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printk(KERN_INFO "%s: attached PHY driver [%s] "
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"(mii_bus:phy_addr=%s, irq=%d)\n",
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dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
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@ -1,20 +0,0 @@
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--- a/drivers/watchdog/mtx-1_wdt.c
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+++ b/drivers/watchdog/mtx-1_wdt.c
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@@ -98,6 +98,8 @@ static void mtx1_wdt_reset(void)
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static void mtx1_wdt_start(void)
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{
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+ unsigned long flags;
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+
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spin_lock_irqsave(&mtx1_wdt_device.lock, flags);
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if (!mtx1_wdt_device.queue) {
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mtx1_wdt_device.queue = 1;
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@@ -110,6 +112,8 @@ static void mtx1_wdt_start(void)
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static int mtx1_wdt_stop(void)
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{
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+ unsigned long flags;
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+
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spin_lock_irqsave(&mtx1_wdt_device.lock, flags);
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if (mtx1_wdt_device.queue) {
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mtx1_wdt_device.queue = 0;
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@ -1,10 +0,0 @@
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--- a/arch/mips/au1000/mtx-1/init.c
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+++ b/arch/mips/au1000/mtx-1/init.c
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@@ -32,6 +32,7 @@
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#include <linux/init.h>
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#include <asm/bootinfo.h>
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+#include <asm/string.h>
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#include <prom.h>
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@ -1,396 +0,0 @@
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--- a/arch/mips/au1000/Kconfig
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+++ b/arch/mips/au1000/Kconfig
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@@ -134,3 +134,4 @@ config SOC_AU1X00
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_APM_EMULATION
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+ select ARCH_REQUIRE_GPIOLIB
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--- a/arch/mips/au1000/common/gpio.c
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+++ b/arch/mips/au1000/common/gpio.c
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
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+ * Copyright (C) 2007-2008, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
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* Architecture specific GPIO support
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*
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* This program is free software; you can redistribute it and/or modify it
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@@ -27,122 +27,222 @@
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* others have a second one : GPIO2
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*/
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+#include <linux/kernel.h>
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#include <linux/module.h>
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+#include <linux/types.h>
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+#include <linux/platform_device.h>
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+#include <linux/gpio.h>
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#include <asm/mach-au1x00/au1000.h>
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-#include <asm/gpio.h>
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+#include <asm/mach-au1x00/gpio.h>
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-#define gpio1 sys
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-#if !defined(CONFIG_SOC_AU1000)
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+struct au1000_gpio_chip {
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+ struct gpio_chip chip;
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+ void __iomem *regbase;
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+};
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-static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
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+#if !defined(CONFIG_SOC_AU1000)
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#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
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-static int au1xxx_gpio2_read(unsigned gpio)
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+/*
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+ * Return GPIO bank 2 level
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+ */
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+static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
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{
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- gpio -= AU1XXX_GPIO_BASE;
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- return ((gpio2->pinstate >> gpio) & 0x01);
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+ u32 mask = 1 << offset;
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+ struct au1000_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
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}
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-static void au1xxx_gpio2_write(unsigned gpio, int value)
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+/*
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+ * Set output GPIO bank 2 level
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+ */
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+static void au1000_gpio2_set(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- gpio -= AU1XXX_GPIO_BASE;
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-
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- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
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+ u32 mask = (!!value) << offset;
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+ struct au1000_gpio_chip *gpch;
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+ unsigned long flags;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+
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+ local_irq_save(flags);
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+ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
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+ gpch->regbase + AU1000_GPIO2_OUT);
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+ local_irq_restore(flags);
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}
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-static int au1xxx_gpio2_direction_input(unsigned gpio)
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+/*
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+ * Set GPIO bank 2 direction to input
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+ */
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+static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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- gpio -= AU1XXX_GPIO_BASE;
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- gpio2->dir &= ~(0x01 << gpio);
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 value;
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+ struct au1000_gpio_chip *gpch;
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+ void __iomem *gpdr;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
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+
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+ local_irq_save(flags);
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+ value = readl(gpdr);
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+ value &= ~mask;
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+ writel(value, gpdr);
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+ local_irq_restore(flags);
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+
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return 0;
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}
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-static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
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+/*
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+ * Set GPIO bank2 direction to output
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+ */
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+static int au1000_gpio2_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- gpio -= AU1XXX_GPIO_BASE;
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- gpio2->dir |= 0x01 << gpio;
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- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct au1000_gpio_chip *gpch;
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+ void __iomem *gpdr;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
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+
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+ local_irq_save(flags);
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+ tmp = readl(gpdr);
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+ tmp |= mask;
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+ writel(tmp, gpdr);
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+ mask = (!!value) << offset;
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+ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
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+ gpch->regbase + AU1000_GPIO2_OUT);
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+ local_irq_restore(flags);
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+
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return 0;
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}
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-
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#endif /* !defined(CONFIG_SOC_AU1000) */
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-static int au1xxx_gpio1_read(unsigned gpio)
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+/*
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+ * Return GPIO bank 2 level
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+ */
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+static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
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{
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- return (gpio1->pinstaterd >> gpio) & 0x01;
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+ u32 mask = 1 << offset;
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+ struct au1000_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ return readl(gpch->regbase + 0x0110) & mask;
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}
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-static void au1xxx_gpio1_write(unsigned gpio, int value)
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+/*
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+ * Set GPIO bank 1 level
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+ */
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+static void au1000_gpio1_set(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ struct au1000_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+
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+ local_irq_save(flags);
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if (value)
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- gpio1->outputset = (0x01 << gpio);
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+ writel(mask, gpch->regbase + 0x0108);
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else
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- /* Output a zero */
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- gpio1->outputclr = (0x01 << gpio);
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+ writel(mask, gpch->regbase + 0x010C);
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+ local_irq_restore(flags);
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}
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-static int au1xxx_gpio1_direction_input(unsigned gpio)
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+/*
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+ * Set GPIO bank 1 direction to input
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+ */
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+static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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- gpio1->pininputen = (0x01 << gpio);
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- return 0;
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-}
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 value;
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+ struct au1000_gpio_chip *gpch;
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+ void __iomem *gpdr;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ gpdr = gpch->regbase + 0x0110;
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+
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+ local_irq_save(flags);
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+ value = readl(gpdr);
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+ value |= mask;
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+ writel(mask, gpdr);
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+ local_irq_restore(flags);
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-static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
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-{
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- gpio1->trioutclr = (0x01 & gpio);
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- au1xxx_gpio1_write(gpio, value);
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return 0;
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}
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-int au1xxx_gpio_get_value(unsigned gpio)
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+/*
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+ * Set GPIO bank 1 direction to output
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+ */
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+static int au1000_gpio1_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- if (gpio >= AU1XXX_GPIO_BASE)
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-#if defined(CONFIG_SOC_AU1000)
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- return 0;
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-#else
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- return au1xxx_gpio2_read(gpio);
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-#endif
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+ unsigned long flags;
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+ u32 mask = 1 << offset;
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+ u32 tmp;
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+ struct au1000_gpio_chip *gpch;
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+ void __iomem *gpdr;
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+
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+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
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+ gpdr = gpch->regbase + 0x0100;
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+
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+ local_irq_save(flags);
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+ tmp = readl(gpdr);
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+ writel(tmp, gpdr);
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+ if (value)
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+ writel(mask, gpch->regbase + 0x0108);
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else
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- return au1xxx_gpio1_read(gpio);
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-}
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-EXPORT_SYMBOL(au1xxx_gpio_get_value);
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+ writel(mask, gpch->regbase + 0x0108);
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+ local_irq_restore(flags);
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-void au1xxx_gpio_set_value(unsigned gpio, int value)
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-{
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- if (gpio >= AU1XXX_GPIO_BASE)
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-#if defined(CONFIG_SOC_AU1000)
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- ;
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-#else
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- au1xxx_gpio2_write(gpio, value);
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-#endif
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- else
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- au1xxx_gpio1_write(gpio, value);
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+ return 0;
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}
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-EXPORT_SYMBOL(au1xxx_gpio_set_value);
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-int au1xxx_gpio_direction_input(unsigned gpio)
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-{
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- if (gpio >= AU1XXX_GPIO_BASE)
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-#if defined(CONFIG_SOC_AU1000)
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- return -ENODEV;
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-#else
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- return au1xxx_gpio2_direction_input(gpio);
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+struct au1000_gpio_chip au1000_gpio_chip[] = {
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+ [0] = {
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+ .regbase = (void __iomem *)SYS_BASE,
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+ .chip = {
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+ .label = "au1000-gpio1",
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+ .direction_input = au1000_gpio1_direction_input,
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+ .direction_output = au1000_gpio1_direction_output,
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+ .get = au1000_gpio1_get,
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+ .set = au1000_gpio1_set,
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+ .base = 0,
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+ .ngpio = 32,
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+ },
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+ },
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+#if !defined(CONFIG_SOC_AU1000)
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+ [1] = {
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+ .regbase = (void __iomem *)GPIO2_BASE,
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+ .chip = {
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+ .label = "au1000-gpio2",
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+ .direction_input = au1000_gpio2_direction_input,
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+ .direction_output = au1000_gpio2_direction_output,
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+ .get = au1000_gpio2_get,
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+ .set = au1000_gpio2_set,
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+ .base = AU1XXX_GPIO_BASE,
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+ .ngpio = 32,
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+ },
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+ },
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#endif
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+};
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- return au1xxx_gpio1_direction_input(gpio);
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-}
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-EXPORT_SYMBOL(au1xxx_gpio_direction_input);
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-
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-int au1xxx_gpio_direction_output(unsigned gpio, int value)
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+int __init au1000_gpio_init(void)
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{
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- if (gpio >= AU1XXX_GPIO_BASE)
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-#if defined(CONFIG_SOC_AU1000)
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- return -ENODEV;
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-#else
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- return au1xxx_gpio2_direction_output(gpio, value);
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+ gpiochip_add(&au1000_gpio_chip[0].chip);
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+#if !defined(CONFIG_SOC_AU1000)
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+ gpiochip_add(&au1000_gpio_chip[1].chip);
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#endif
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- return au1xxx_gpio1_direction_output(gpio, value);
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+ return 0;
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}
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-EXPORT_SYMBOL(au1xxx_gpio_direction_output);
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+arch_initcall(au1000_gpio_init);
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--- a/include/asm-mips/mach-au1x00/gpio.h
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+++ b/include/asm-mips/mach-au1x00/gpio.h
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@@ -1,69 +1,21 @@
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#ifndef _AU1XXX_GPIO_H_
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#define _AU1XXX_GPIO_H_
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-#include <linux/types.h>
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-
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#define AU1XXX_GPIO_BASE 200
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-struct au1x00_gpio2 {
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- u32 dir;
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- u32 reserved;
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- u32 output;
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- u32 pinstate;
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- u32 inten;
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- u32 enable;
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-};
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-
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-extern int au1xxx_gpio_get_value(unsigned gpio);
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-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
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-extern int au1xxx_gpio_direction_input(unsigned gpio);
|
||||
-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
|
||||
-
|
||||
-
|
||||
-/* Wrappers for the arch-neutral GPIO API */
|
||||
-
|
||||
-static inline int gpio_request(unsigned gpio, const char *label)
|
||||
-{
|
||||
- /* Not yet implemented */
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-static inline void gpio_free(unsigned gpio)
|
||||
-{
|
||||
- /* Not yet implemented */
|
||||
-}
|
||||
-
|
||||
-static inline int gpio_direction_input(unsigned gpio)
|
||||
-{
|
||||
- return au1xxx_gpio_direction_input(gpio);
|
||||
-}
|
||||
-
|
||||
-static inline int gpio_direction_output(unsigned gpio, int value)
|
||||
-{
|
||||
- return au1xxx_gpio_direction_output(gpio, value);
|
||||
-}
|
||||
-
|
||||
-static inline int gpio_get_value(unsigned gpio)
|
||||
-{
|
||||
- return au1xxx_gpio_get_value(gpio);
|
||||
-}
|
||||
-
|
||||
-static inline void gpio_set_value(unsigned gpio, int value)
|
||||
-{
|
||||
- au1xxx_gpio_set_value(gpio, value);
|
||||
-}
|
||||
-
|
||||
-static inline int gpio_to_irq(unsigned gpio)
|
||||
-{
|
||||
- return gpio;
|
||||
-}
|
||||
-
|
||||
-static inline int irq_to_gpio(unsigned irq)
|
||||
-{
|
||||
- return irq;
|
||||
-}
|
||||
+#define AU1000_GPIO2_DIR 0x00
|
||||
+#define AU1000_GPIO2_RSVD 0x04
|
||||
+#define AU1000_GPIO2_OUT 0x08
|
||||
+#define AU1000_GPIO2_ST 0x0C
|
||||
+#define AU1000_GPIO2_INT 0x10
|
||||
+#define AU1000_GPIO2_EN 0x14
|
||||
+
|
||||
+#define gpio_get_value __gpio_get_value
|
||||
+#define gpio_set_value __gpio_set_value
|
||||
+
|
||||
+#define gpio_to_irq(gpio) NULL
|
||||
+#define irq_to_gpio(irq) NULL
|
||||
|
||||
-/* For cansleep */
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* _AU1XXX_GPIO_H_ */
|
||||
Loading…
Reference in New Issue
Block a user