uboot-rockchip: add suport for Radxa ROCK Pi E
Add uboot support for Radxa ROCK Pi E, rockchip rk3328 board.
Add pre-built files to fix swig dependencies.
Specification:
- CPU: Rockchip RK3328 64-bit Quad-core
- RAM: DDR3 256MB ~ 2GB
- Network:
1 x 10/100/1000M Ethernet
1 x 10/100M Ethernet
- USB Host:
1 x USB3.0 Type A HOST
1 x USB2.0 OTG (40-pin pin-header)
- Wireless:
RTL8723DU/RTL8821CU
- Power Supply: Type-C 5V
Installation:
- Write image to SD Card or EMMC with dd
- Boot ROCK Pi E from the SD Card
Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
This commit is contained in:
Jayantajit Gogoi
Jayantajit Gogoi
parent
77c45ddd86
commit
18b6bae851
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@ -73,6 +73,13 @@ define U-Boot/rock64-rk3328
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pine64_rock64
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endef
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define U-Boot/rock-pi-e-rk3328
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$(U-Boot/rk3328/Default)
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NAME:=ROCK Pi E
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BUILD_DEVICES:= \
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radxa_rock-pi-e
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endef
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# RK3399 boards
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define U-Boot/rk3399/Default
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@ -119,7 +126,8 @@ UBOOT_TARGETS := \
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orangepi-r1-plus-rk3328 \
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orangepi-r1-plus-lts-rk3328 \
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roc-cc-rk3328 \
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rock64-rk3328
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rock64-rk3328 \
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rock-pi-e-rk3328
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UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
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@ -0,0 +1,24 @@
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/*
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* DO NOT MODIFY
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*
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* Declares externs for all device/uclass instances.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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/* driver declarations - these allow DM_DRIVER_GET() to be used */
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extern U_BOOT_DRIVER(rockchip_rk3328_cru);
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extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
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extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
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extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
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extern U_BOOT_DRIVER(ns16550_serial);
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extern U_BOOT_DRIVER(rockchip_rk3328_grf);
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/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
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extern UCLASS_DRIVER(clk);
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extern UCLASS_DRIVER(mmc);
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extern UCLASS_DRIVER(ram);
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extern UCLASS_DRIVER(serial);
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extern UCLASS_DRIVER(syscon);
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@ -0,0 +1,189 @@
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/*
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* DO NOT MODIFY
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*
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* Declares the U_BOOT_DRIVER() records and platform data.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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/* Allow use of U_BOOT_DRVINFO() in this file */
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#define DT_PLAT_C
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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/*
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* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
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*
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* idx driver_info driver
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* --- -------------------- --------------------
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* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
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* 1: dmc rockchip_rk3328_dmc
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* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
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* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
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* 4: serial_at_ff130000 ns16550_serial
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* 5: syscon_at_ff100000 rockchip_rk3328_grf
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* --- -------------------- --------------------
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*/
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/*
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* Node /clock-controller@ff440000 index 0
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* driver rockchip_rk3328_cru parent None
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*/
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static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
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.reg = {0xff440000, 0x1000},
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.rockchip_grf = 0x38,
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};
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U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
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.name = "rockchip_rk3328_cru",
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.plat = &dtv_clock_controller_at_ff440000,
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.plat_size = sizeof(dtv_clock_controller_at_ff440000),
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.parent_idx = -1,
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};
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/*
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* Node /dmc index 1
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* driver rockchip_rk3328_dmc parent None
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*/
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static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
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.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
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0xff720000, 0x1000, 0xff798000, 0x1000},
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.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
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0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15,
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0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0,
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0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8,
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0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4,
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0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c,
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0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180,
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0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0,
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0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490,
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0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c,
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0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
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0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
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0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
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0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
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0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
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0x77, 0x77, 0x79, 0x9},
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};
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U_BOOT_DRVINFO(dmc) = {
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.name = "rockchip_rk3328_dmc",
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.plat = &dtv_dmc,
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.plat_size = sizeof(dtv_dmc),
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.parent_idx = -1,
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};
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/*
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* Node /mmc@ff500000 index 2
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* driver rockchip_rk3288_dw_mshc parent None
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*/
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static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
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.bus_width = 0x4,
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.cap_mmc_highspeed = true,
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.cap_sd_highspeed = true,
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.card_detect_delay = 0xc8,
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.clocks = {
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{0, {317}},
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{0, {33}},
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{0, {74}},
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{0, {78}},},
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.disable_wp = true,
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.fifo_depth = 0x100,
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.interrupts = {0x0, 0xc, 0x4},
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.max_frequency = 0x8f0d180,
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.num_slots = 0x1,
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.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
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.pinctrl_names = "default",
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.reg = {0xff500000, 0x4000},
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.supports_sd = true,
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.u_boot_spl_fifo_mode = true,
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.vmmc_supply = 0x49,
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};
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U_BOOT_DRVINFO(mmc_at_ff500000) = {
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.name = "rockchip_rk3288_dw_mshc",
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.plat = &dtv_mmc_at_ff500000,
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.plat_size = sizeof(dtv_mmc_at_ff500000),
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.parent_idx = -1,
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};
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/*
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* Node /mmc@ff520000 index 3
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* driver rockchip_rk3288_dw_mshc parent None
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*/
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static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
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.bus_width = 0x8,
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.cap_mmc_highspeed = true,
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.clocks = {
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{0, {319}},
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{0, {35}},
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{0, {76}},
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{0, {80}},},
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.disable_wp = true,
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.fifo_depth = 0x100,
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.interrupts = {0x0, 0xe, 0x4},
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.max_frequency = 0x8f0d180,
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.mmc_hs200_1_8v = true,
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.non_removable = true,
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.num_slots = 0x1,
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.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x0},
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.pinctrl_names = "default",
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.reg = {0xff520000, 0x4000},
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.supports_emmc = true,
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.u_boot_spl_fifo_mode = true,
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.vmmc_supply = 0x1c,
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.vqmmc_supply = 0x1d,
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};
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U_BOOT_DRVINFO(mmc_at_ff520000) = {
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.name = "rockchip_rk3288_dw_mshc",
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.plat = &dtv_mmc_at_ff520000,
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.plat_size = sizeof(dtv_mmc_at_ff520000),
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.parent_idx = -1,
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};
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/*
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* Node /serial@ff130000 index 4
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* driver ns16550_serial parent None
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*/
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static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
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.clock_frequency = 0x16e3600,
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.clocks = {
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{0, {40}},
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{0, {212}},},
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.dma_names = {"tx", "rx"},
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.dmas = {0x10, 0x6, 0x10, 0x7},
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.interrupts = {0x0, 0x39, 0x4},
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.pinctrl_0 = 0x24,
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.pinctrl_names = "default",
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.reg = {0xff130000, 0x100},
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.reg_io_width = 0x4,
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.reg_shift = 0x2,
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};
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U_BOOT_DRVINFO(serial_at_ff130000) = {
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.name = "ns16550_serial",
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.plat = &dtv_serial_at_ff130000,
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.plat_size = sizeof(dtv_serial_at_ff130000),
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.parent_idx = -1,
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};
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/*
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* Node /syscon@ff100000 index 5
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* driver rockchip_rk3328_grf parent None
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*/
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static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
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.reg = {0xff100000, 0x1000},
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};
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U_BOOT_DRVINFO(syscon_at_ff100000) = {
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.name = "rockchip_rk3328_grf",
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.plat = &dtv_syscon_at_ff100000,
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.plat_size = sizeof(dtv_syscon_at_ff100000),
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.parent_idx = -1,
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};
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@ -0,0 +1,54 @@
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/*
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* DO NOT MODIFY
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*
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* Defines the structs used to hold devicetree data.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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#include <stdbool.h>
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#include <linux/libfdt.h>
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struct dtd_ns16550_serial {
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fdt32_t clock_frequency;
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struct phandle_1_arg clocks[2];
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const char * dma_names[2];
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fdt32_t dmas[4];
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fdt32_t interrupts[3];
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fdt32_t pinctrl_0;
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const char * pinctrl_names;
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fdt64_t reg[2];
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fdt32_t reg_io_width;
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fdt32_t reg_shift;
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};
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struct dtd_rockchip_rk3288_dw_mshc {
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fdt32_t bus_width;
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bool cap_mmc_highspeed;
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bool cap_sd_highspeed;
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fdt32_t card_detect_delay;
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struct phandle_1_arg clocks[4];
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bool disable_wp;
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fdt32_t fifo_depth;
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fdt32_t interrupts[3];
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fdt32_t max_frequency;
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bool mmc_hs200_1_8v;
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bool non_removable;
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fdt32_t num_slots;
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fdt32_t pinctrl_0[4];
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const char * pinctrl_names;
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fdt64_t reg[2];
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bool supports_emmc;
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bool supports_sd;
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bool u_boot_spl_fifo_mode;
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fdt32_t vmmc_supply;
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fdt32_t vqmmc_supply;
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};
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struct dtd_rockchip_rk3328_cru {
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fdt64_t reg[2];
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fdt32_t rockchip_grf;
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};
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struct dtd_rockchip_rk3328_dmc {
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fdt64_t reg[12];
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fdt32_t rockchip_sdram_params[196];
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};
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struct dtd_rockchip_rk3328_grf {
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fdt64_t reg[2];
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};
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