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qualcommax: ipq8074-ess: move switch to ess-instance node
It seems that newer SSDK is now expecting the switch node to be a subnode of "ess-instance" node which also contains "num_devices" as the number of switches as you can also have external switches connected. Asus RT-AX89X is even more peculiar as its bootloader has a hardcoded path to enable if on that revision there is an AQR113 connected to port 6 of the switch. So, lets move the current switch node under ess-instance as otherwise it seems that SSDK is having some issues parsing the UNIPHY mode properly as I am getting the following: [ 6.981404] _adpt_hppe_instance1_mode_get[3275]:ERROR:port 6 doesn't support port_interface_mode 9 Which should not happen as that port has the mode set to 13. Link: https://github.com/openwrt/openwrt/pull/15840 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
parent
d55f4aeee0
commit
157a33402d
@ -17,407 +17,413 @@
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};
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&soc {
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switch: ess-switch@3a000000 {
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compatible = "qcom,ess-switch-ipq807x";
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reg = <0x3a000000 0x1000000>;
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switch_access_mode = "local bus";
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switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
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switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
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clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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<&gcc GCC_CMN_12GPLL_SYS_CLK>,
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<&gcc GCC_UNIPHY0_AHB_CLK>,
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<&gcc GCC_UNIPHY0_SYS_CLK>,
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<&gcc GCC_UNIPHY1_AHB_CLK>,
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<&gcc GCC_UNIPHY1_SYS_CLK>,
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<&gcc GCC_UNIPHY2_AHB_CLK>,
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<&gcc GCC_UNIPHY2_SYS_CLK>,
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<&gcc GCC_PORT1_MAC_CLK>,
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<&gcc GCC_PORT2_MAC_CLK>,
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<&gcc GCC_PORT3_MAC_CLK>,
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<&gcc GCC_PORT4_MAC_CLK>,
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<&gcc GCC_PORT5_MAC_CLK>,
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<&gcc GCC_PORT6_MAC_CLK>,
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<&gcc GCC_NSS_PPE_CLK>,
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<&gcc GCC_NSS_PPE_CFG_CLK>,
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<&gcc GCC_NSSNOC_PPE_CLK>,
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<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
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<&gcc GCC_NSS_EDMA_CLK>,
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<&gcc GCC_NSS_EDMA_CFG_CLK>,
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<&gcc GCC_NSS_PPE_IPE_CLK>,
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<&gcc GCC_NSS_PPE_BTQ_CLK>,
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<&gcc GCC_MDIO_AHB_CLK>,
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<&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
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<&gcc GCC_NSS_CRYPTO_CLK>,
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<&gcc GCC_NSS_IMEM_CLK>,
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<&gcc GCC_NSS_PTP_REF_CLK>,
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<&gcc GCC_NSS_PORT1_RX_CLK>,
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<&gcc GCC_NSS_PORT1_TX_CLK>,
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<&gcc GCC_NSS_PORT2_RX_CLK>,
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<&gcc GCC_NSS_PORT2_TX_CLK>,
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<&gcc GCC_NSS_PORT3_RX_CLK>,
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<&gcc GCC_NSS_PORT3_TX_CLK>,
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<&gcc GCC_NSS_PORT4_RX_CLK>,
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<&gcc GCC_NSS_PORT4_TX_CLK>,
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<&gcc GCC_NSS_PORT5_RX_CLK>,
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<&gcc GCC_NSS_PORT5_TX_CLK>,
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<&gcc GCC_NSS_PORT6_RX_CLK>,
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<&gcc GCC_NSS_PORT6_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
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<&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
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<&gcc NSS_PORT5_RX_CLK_SRC>,
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<&gcc NSS_PORT5_TX_CLK_SRC>;
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clock-names = "cmn_ahb_clk", "cmn_sys_clk",
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"uniphy0_ahb_clk", "uniphy0_sys_clk",
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"uniphy1_ahb_clk", "uniphy1_sys_clk",
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"uniphy2_ahb_clk", "uniphy2_sys_clk",
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"port1_mac_clk", "port2_mac_clk",
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"port3_mac_clk", "port4_mac_clk",
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"port5_mac_clk", "port6_mac_clk",
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"nss_ppe_clk", "nss_ppe_cfg_clk",
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"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
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"nss_edma_clk", "nss_edma_cfg_clk",
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"nss_ppe_ipe_clk", "nss_ppe_btq_clk",
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"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
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"gcc_nssnoc_snoc_clk",
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"gcc_mem_noc_nss_axi_clk",
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"gcc_nss_crypto_clk",
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"gcc_nss_imem_clk",
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"gcc_nss_ptp_ref_clk",
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"nss_port1_rx_clk", "nss_port1_tx_clk",
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"nss_port2_rx_clk", "nss_port2_tx_clk",
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"nss_port3_rx_clk", "nss_port3_tx_clk",
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"nss_port4_rx_clk", "nss_port4_tx_clk",
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"nss_port5_rx_clk", "nss_port5_tx_clk",
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"nss_port6_rx_clk", "nss_port6_tx_clk",
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"uniphy0_port1_rx_clk",
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"uniphy0_port1_tx_clk",
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"uniphy0_port2_rx_clk",
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"uniphy0_port2_tx_clk",
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"uniphy0_port3_rx_clk",
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"uniphy0_port3_tx_clk",
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"uniphy0_port4_rx_clk",
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"uniphy0_port4_tx_clk",
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"uniphy0_port5_rx_clk",
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"uniphy0_port5_tx_clk",
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"uniphy1_port5_rx_clk",
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"uniphy1_port5_tx_clk",
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"uniphy2_port6_rx_clk",
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"uniphy2_port6_tx_clk",
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"nss_port5_rx_clk_src",
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"nss_port5_tx_clk_src";
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resets = <&gcc GCC_PPE_FULL_RESET>,
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<&gcc GCC_UNIPHY0_SOFT_RESET>,
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<&gcc GCC_UNIPHY0_XPCS_RESET>,
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<&gcc GCC_UNIPHY1_SOFT_RESET>,
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<&gcc GCC_UNIPHY1_XPCS_RESET>,
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<&gcc GCC_UNIPHY2_SOFT_RESET>,
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<&gcc GCC_UNIPHY2_XPCS_RESET>,
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<&gcc GCC_NSSPORT1_RESET>,
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<&gcc GCC_NSSPORT2_RESET>,
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<&gcc GCC_NSSPORT3_RESET>,
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<&gcc GCC_NSSPORT4_RESET>,
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<&gcc GCC_NSSPORT5_RESET>,
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<&gcc GCC_NSSPORT6_RESET>;
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reset-names = "ppe_rst", "uniphy0_soft_rst",
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"uniphy0_xpcs_rst", "uniphy1_soft_rst",
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"uniphy1_xpcs_rst", "uniphy2_soft_rst",
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"uniphy2_xpcs_rst", "nss_port1_rst",
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"nss_port2_rst", "nss_port3_rst",
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"nss_port4_rst", "nss_port5_rst",
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"nss_port6_rst";
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mdio-bus = <&mdio>;
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ess_instance: ess-instance {
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#address-cells = <1>;
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#size-cells = <1>;
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num_devices = <1>;
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switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
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switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
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switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
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switch: ess-switch@3a000000 {
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compatible = "qcom,ess-switch-ipq807x";
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reg = <0x3a000000 0x1000000>;
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switch_access_mode = "local bus";
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switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
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switch_inner_bmp = <ESS_PORT7>; /*inner port bitmap*/
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clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
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<&gcc GCC_CMN_12GPLL_SYS_CLK>,
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<&gcc GCC_UNIPHY0_AHB_CLK>,
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<&gcc GCC_UNIPHY0_SYS_CLK>,
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<&gcc GCC_UNIPHY1_AHB_CLK>,
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<&gcc GCC_UNIPHY1_SYS_CLK>,
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<&gcc GCC_UNIPHY2_AHB_CLK>,
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<&gcc GCC_UNIPHY2_SYS_CLK>,
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<&gcc GCC_PORT1_MAC_CLK>,
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<&gcc GCC_PORT2_MAC_CLK>,
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<&gcc GCC_PORT3_MAC_CLK>,
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<&gcc GCC_PORT4_MAC_CLK>,
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<&gcc GCC_PORT5_MAC_CLK>,
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<&gcc GCC_PORT6_MAC_CLK>,
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<&gcc GCC_NSS_PPE_CLK>,
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<&gcc GCC_NSS_PPE_CFG_CLK>,
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<&gcc GCC_NSSNOC_PPE_CLK>,
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<&gcc GCC_NSSNOC_PPE_CFG_CLK>,
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<&gcc GCC_NSS_EDMA_CLK>,
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<&gcc GCC_NSS_EDMA_CFG_CLK>,
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<&gcc GCC_NSS_PPE_IPE_CLK>,
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<&gcc GCC_NSS_PPE_BTQ_CLK>,
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<&gcc GCC_MDIO_AHB_CLK>,
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<&gcc GCC_NSS_NOC_CLK>,
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<&gcc GCC_NSSNOC_SNOC_CLK>,
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<&gcc GCC_MEM_NOC_NSS_AXI_CLK>,
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<&gcc GCC_NSS_CRYPTO_CLK>,
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<&gcc GCC_NSS_IMEM_CLK>,
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<&gcc GCC_NSS_PTP_REF_CLK>,
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<&gcc GCC_NSS_PORT1_RX_CLK>,
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<&gcc GCC_NSS_PORT1_TX_CLK>,
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<&gcc GCC_NSS_PORT2_RX_CLK>,
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<&gcc GCC_NSS_PORT2_TX_CLK>,
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<&gcc GCC_NSS_PORT3_RX_CLK>,
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<&gcc GCC_NSS_PORT3_TX_CLK>,
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<&gcc GCC_NSS_PORT4_RX_CLK>,
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<&gcc GCC_NSS_PORT4_TX_CLK>,
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<&gcc GCC_NSS_PORT5_RX_CLK>,
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<&gcc GCC_NSS_PORT5_TX_CLK>,
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<&gcc GCC_NSS_PORT6_RX_CLK>,
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<&gcc GCC_NSS_PORT6_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
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<&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
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<&gcc GCC_UNIPHY2_PORT6_RX_CLK>,
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<&gcc GCC_UNIPHY2_PORT6_TX_CLK>,
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<&gcc NSS_PORT5_RX_CLK_SRC>,
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<&gcc NSS_PORT5_TX_CLK_SRC>;
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clock-names = "cmn_ahb_clk", "cmn_sys_clk",
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"uniphy0_ahb_clk", "uniphy0_sys_clk",
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"uniphy1_ahb_clk", "uniphy1_sys_clk",
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"uniphy2_ahb_clk", "uniphy2_sys_clk",
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"port1_mac_clk", "port2_mac_clk",
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"port3_mac_clk", "port4_mac_clk",
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"port5_mac_clk", "port6_mac_clk",
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"nss_ppe_clk", "nss_ppe_cfg_clk",
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"nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
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"nss_edma_clk", "nss_edma_cfg_clk",
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"nss_ppe_ipe_clk", "nss_ppe_btq_clk",
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"gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
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"gcc_nssnoc_snoc_clk",
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"gcc_mem_noc_nss_axi_clk",
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"gcc_nss_crypto_clk",
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"gcc_nss_imem_clk",
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"gcc_nss_ptp_ref_clk",
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"nss_port1_rx_clk", "nss_port1_tx_clk",
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"nss_port2_rx_clk", "nss_port2_tx_clk",
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"nss_port3_rx_clk", "nss_port3_tx_clk",
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"nss_port4_rx_clk", "nss_port4_tx_clk",
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"nss_port5_rx_clk", "nss_port5_tx_clk",
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"nss_port6_rx_clk", "nss_port6_tx_clk",
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"uniphy0_port1_rx_clk",
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"uniphy0_port1_tx_clk",
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"uniphy0_port2_rx_clk",
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"uniphy0_port2_tx_clk",
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"uniphy0_port3_rx_clk",
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"uniphy0_port3_tx_clk",
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"uniphy0_port4_rx_clk",
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"uniphy0_port4_tx_clk",
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"uniphy0_port5_rx_clk",
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"uniphy0_port5_tx_clk",
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"uniphy1_port5_rx_clk",
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"uniphy1_port5_tx_clk",
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"uniphy2_port6_rx_clk",
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"uniphy2_port6_tx_clk",
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"nss_port5_rx_clk_src",
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"nss_port5_tx_clk_src";
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resets = <&gcc GCC_PPE_FULL_RESET>,
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<&gcc GCC_UNIPHY0_SOFT_RESET>,
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<&gcc GCC_UNIPHY0_XPCS_RESET>,
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<&gcc GCC_UNIPHY1_SOFT_RESET>,
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<&gcc GCC_UNIPHY1_XPCS_RESET>,
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<&gcc GCC_UNIPHY2_SOFT_RESET>,
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<&gcc GCC_UNIPHY2_XPCS_RESET>,
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<&gcc GCC_NSSPORT1_RESET>,
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<&gcc GCC_NSSPORT2_RESET>,
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<&gcc GCC_NSSPORT3_RESET>,
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<&gcc GCC_NSSPORT4_RESET>,
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<&gcc GCC_NSSPORT5_RESET>,
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<&gcc GCC_NSSPORT6_RESET>;
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reset-names = "ppe_rst", "uniphy0_soft_rst",
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"uniphy0_xpcs_rst", "uniphy1_soft_rst",
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"uniphy1_xpcs_rst", "uniphy2_soft_rst",
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"uniphy2_xpcs_rst", "nss_port1_rst",
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"nss_port2_rst", "nss_port3_rst",
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"nss_port4_rst", "nss_port5_rst",
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"nss_port6_rst";
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mdio-bus = <&mdio>;
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bm_tick_mode = <0>; /* bm tick mode */
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tm_tick_mode = <0>; /* tm tick mode */
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switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
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switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
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switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
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status = "disabled";
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bm_tick_mode = <0>; /* bm tick mode */
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tm_tick_mode = <0>; /* tm tick mode */
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port_scheduler_resource {
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port@0 {
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port_id = <0>;
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ucast_queue = <0 143>;
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mcast_queue = <256 271>;
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l0sp = <0 35>;
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l0cdrr = <0 47>;
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l0edrr = <0 47>;
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l1cdrr = <0 7>;
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l1edrr = <0 7>;
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};
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port@1 {
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port_id = <1>;
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ucast_queue = <144 159>;
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mcast_queue = <272 275>;
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l0sp = <36 39>;
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l0cdrr = <48 63>;
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l0edrr = <48 63>;
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l1cdrr = <8 11>;
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l1edrr = <8 11>;
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};
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port@2 {
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port_id = <2>;
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ucast_queue = <160 175>;
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mcast_queue = <276 279>;
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l0sp = <40 43>;
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l0cdrr = <64 79>;
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l0edrr = <64 79>;
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l1cdrr = <12 15>;
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l1edrr = <12 15>;
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};
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port@3 {
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port_id = <3>;
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ucast_queue = <176 191>;
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mcast_queue = <280 283>;
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l0sp = <44 47>;
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l0cdrr = <80 95>;
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l0edrr = <80 95>;
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l1cdrr = <16 19>;
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l1edrr = <16 19>;
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};
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port@4 {
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port_id = <4>;
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ucast_queue = <192 207>;
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mcast_queue = <284 287>;
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l0sp = <48 51>;
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l0cdrr = <96 111>;
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l0edrr = <96 111>;
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l1cdrr = <20 23>;
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l1edrr = <20 23>;
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};
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port@5 {
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port_id = <5>;
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ucast_queue = <208 223>;
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mcast_queue = <288 291>;
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l0sp = <52 55>;
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l0cdrr = <112 127>;
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l0edrr = <112 127>;
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l1cdrr = <24 27>;
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l1edrr = <24 27>;
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};
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port@6 {
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port_id = <6>;
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ucast_queue = <224 239>;
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mcast_queue = <292 295>;
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l0sp = <56 59>;
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l0cdrr = <128 143>;
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l0edrr = <128 143>;
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l1cdrr = <28 31>;
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l1edrr = <28 31>;
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};
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port@7 {
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port_id = <7>;
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ucast_queue = <240 255>;
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mcast_queue = <296 299>;
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l0sp = <60 63>;
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l0cdrr = <144 159>;
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l0edrr = <144 159>;
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l1cdrr = <32 35>;
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l1edrr = <32 35>;
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};
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};
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port_scheduler_config {
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port@0 {
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||||
port_id = <0>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <0 1>; /*L0 SPs*/
|
||||
/*cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0>;
|
||||
};
|
||||
status = "disabled";
|
||||
|
||||
port_scheduler_resource {
|
||||
port@0 {
|
||||
port_id = <0>;
|
||||
ucast_queue = <0 143>;
|
||||
mcast_queue = <256 271>;
|
||||
l0sp = <0 35>;
|
||||
l0cdrr = <0 47>;
|
||||
l0edrr = <0 47>;
|
||||
l1cdrr = <0 7>;
|
||||
l1edrr = <0 7>;
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
/*unicast queues*/
|
||||
ucast_queue = <0 4 8>;
|
||||
/*multicast queues*/
|
||||
mcast_queue = <256 260>;
|
||||
/*sp cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0 0>;
|
||||
};
|
||||
group@1 {
|
||||
ucast_queue = <1 5 9>;
|
||||
mcast_queue = <257 261>;
|
||||
cfg = <0 1 1 1 1>;
|
||||
};
|
||||
group@2 {
|
||||
ucast_queue = <2 6 10>;
|
||||
mcast_queue = <258 262>;
|
||||
cfg = <0 2 2 2 2>;
|
||||
};
|
||||
group@3 {
|
||||
ucast_queue = <3 7 11>;
|
||||
mcast_queue = <259 263>;
|
||||
cfg = <0 3 3 3 3>;
|
||||
};
|
||||
port@1 {
|
||||
port_id = <1>;
|
||||
ucast_queue = <144 159>;
|
||||
mcast_queue = <272 275>;
|
||||
l0sp = <36 39>;
|
||||
l0cdrr = <48 63>;
|
||||
l0edrr = <48 63>;
|
||||
l1cdrr = <8 11>;
|
||||
l1edrr = <8 11>;
|
||||
};
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
ucast_queue = <160 175>;
|
||||
mcast_queue = <276 279>;
|
||||
l0sp = <40 43>;
|
||||
l0cdrr = <64 79>;
|
||||
l0edrr = <64 79>;
|
||||
l1cdrr = <12 15>;
|
||||
l1edrr = <12 15>;
|
||||
};
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
ucast_queue = <176 191>;
|
||||
mcast_queue = <280 283>;
|
||||
l0sp = <44 47>;
|
||||
l0cdrr = <80 95>;
|
||||
l0edrr = <80 95>;
|
||||
l1cdrr = <16 19>;
|
||||
l1edrr = <16 19>;
|
||||
};
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
ucast_queue = <192 207>;
|
||||
mcast_queue = <284 287>;
|
||||
l0sp = <48 51>;
|
||||
l0cdrr = <96 111>;
|
||||
l0edrr = <96 111>;
|
||||
l1cdrr = <20 23>;
|
||||
l1edrr = <20 23>;
|
||||
};
|
||||
port@5 {
|
||||
port_id = <5>;
|
||||
ucast_queue = <208 223>;
|
||||
mcast_queue = <288 291>;
|
||||
l0sp = <52 55>;
|
||||
l0cdrr = <112 127>;
|
||||
l0edrr = <112 127>;
|
||||
l1cdrr = <24 27>;
|
||||
l1edrr = <24 27>;
|
||||
};
|
||||
port@6 {
|
||||
port_id = <6>;
|
||||
ucast_queue = <224 239>;
|
||||
mcast_queue = <292 295>;
|
||||
l0sp = <56 59>;
|
||||
l0cdrr = <128 143>;
|
||||
l0edrr = <128 143>;
|
||||
l1cdrr = <28 31>;
|
||||
l1edrr = <28 31>;
|
||||
};
|
||||
port@7 {
|
||||
port_id = <7>;
|
||||
ucast_queue = <240 255>;
|
||||
mcast_queue = <296 299>;
|
||||
l0sp = <60 63>;
|
||||
l0cdrr = <144 159>;
|
||||
l0edrr = <144 159>;
|
||||
l1cdrr = <32 35>;
|
||||
l1edrr = <32 35>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
port_id = <1>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <36>;
|
||||
cfg = <0 8 0 8>;
|
||||
port_scheduler_config {
|
||||
port@0 {
|
||||
port_id = <0>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <0 1>; /*L0 SPs*/
|
||||
/*cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0>;
|
||||
};
|
||||
};
|
||||
group@1 {
|
||||
sp = <37>;
|
||||
cfg = <1 9 1 9>;
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
/*unicast queues*/
|
||||
ucast_queue = <0 4 8>;
|
||||
/*multicast queues*/
|
||||
mcast_queue = <256 260>;
|
||||
/*sp cpri cdrr epri edrr*/
|
||||
cfg = <0 0 0 0 0>;
|
||||
};
|
||||
group@1 {
|
||||
ucast_queue = <1 5 9>;
|
||||
mcast_queue = <257 261>;
|
||||
cfg = <0 1 1 1 1>;
|
||||
};
|
||||
group@2 {
|
||||
ucast_queue = <2 6 10>;
|
||||
mcast_queue = <258 262>;
|
||||
cfg = <0 2 2 2 2>;
|
||||
};
|
||||
group@3 {
|
||||
ucast_queue = <3 7 11>;
|
||||
mcast_queue = <259 263>;
|
||||
cfg = <0 3 3 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <144>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <272>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <36 0 48 0 48>;
|
||||
port@1 {
|
||||
port_id = <1>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <36>;
|
||||
cfg = <0 8 0 8>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <37>;
|
||||
cfg = <1 9 1 9>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <144>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <272>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <36 0 48 0 48>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <40>;
|
||||
cfg = <0 12 0 12>;
|
||||
port@2 {
|
||||
port_id = <2>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <40>;
|
||||
cfg = <0 12 0 12>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <41>;
|
||||
cfg = <1 13 1 13>;
|
||||
};
|
||||
};
|
||||
group@1 {
|
||||
sp = <41>;
|
||||
cfg = <1 13 1 13>;
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <160>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <276>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <40 0 64 0 64>;
|
||||
};
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <160>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <276>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <40 0 64 0 64>;
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <44>;
|
||||
cfg = <0 16 0 16>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <45>;
|
||||
cfg = <1 17 1 17>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <176>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <280>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <44 0 80 0 80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@3 {
|
||||
port_id = <3>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <44>;
|
||||
cfg = <0 16 0 16>;
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <48>;
|
||||
cfg = <0 20 0 20>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <49>;
|
||||
cfg = <1 21 1 21>;
|
||||
};
|
||||
};
|
||||
group@1 {
|
||||
sp = <45>;
|
||||
cfg = <1 17 1 17>;
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <192>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <284>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <48 0 96 0 96>;
|
||||
};
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <176>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <280>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <44 0 80 0 80>;
|
||||
port@5 {
|
||||
port_id = <5>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <52>;
|
||||
cfg = <0 24 0 24>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <53>;
|
||||
cfg = <1 25 1 25>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <208>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <288>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <52 0 112 0 112>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@4 {
|
||||
port_id = <4>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <48>;
|
||||
cfg = <0 20 0 20>;
|
||||
port@6 {
|
||||
port_id = <6>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <56>;
|
||||
cfg = <0 28 0 28>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <57>;
|
||||
cfg = <1 29 1 29>;
|
||||
};
|
||||
};
|
||||
group@1 {
|
||||
sp = <49>;
|
||||
cfg = <1 21 1 21>;
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <224>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <292>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <56 0 128 0 128>;
|
||||
};
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <192>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <284>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <48 0 96 0 96>;
|
||||
port@7 {
|
||||
port_id = <7>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <60>;
|
||||
cfg = <0 32 0 32>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <61>;
|
||||
cfg = <1 33 1 33>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
port@5 {
|
||||
port_id = <5>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <52>;
|
||||
cfg = <0 24 0 24>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <53>;
|
||||
cfg = <1 25 1 25>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <208>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <288>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <52 0 112 0 112>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@6 {
|
||||
port_id = <6>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <56>;
|
||||
cfg = <0 28 0 28>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <57>;
|
||||
cfg = <1 29 1 29>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <224>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <292>;
|
||||
mcast_loop_pri = <4>;
|
||||
cfg = <56 0 128 0 128>;
|
||||
};
|
||||
};
|
||||
};
|
||||
port@7 {
|
||||
port_id = <7>;
|
||||
l1scheduler {
|
||||
group@0 {
|
||||
sp = <60>;
|
||||
cfg = <0 32 0 32>;
|
||||
};
|
||||
group@1 {
|
||||
sp = <61>;
|
||||
cfg = <1 33 1 33>;
|
||||
};
|
||||
};
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <240>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <296>;
|
||||
cfg = <60 0 144 0 144>;
|
||||
l0scheduler {
|
||||
group@0 {
|
||||
ucast_queue = <240>;
|
||||
ucast_loop_pri = <16>;
|
||||
mcast_queue = <296>;
|
||||
cfg = <60 0 144 0 144>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user