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mediatek: switch over to extended upstream eip97 driver 

Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin 2020-06-04 14:20:34 +02:00
parent 3559b46b62
commit 127ad76311
3 changed files with 5514 additions and 0 deletions
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5464
target/linux/mediatek/patches-5.4/0500-v5.6-crypto-backport-inside-secure.patch Normal file
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27
target/linux/mediatek/patches-5.4/0501-crypto-add-eip97-inside-secure-support.patch Normal file
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@ -0,0 +1,27 @@
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -595,6 +595,14 @@
val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
}
+ /*
+ * Set maximum number of TX commands to 2^5 = 32 for EIP97 HW2.1
+ */
+ else {
+ val = 0;
+ val |= EIP97_MST_CTRL_TX_MAX_CMD(5);
+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
+ }
/* Configure wr/rd cache values */
writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
--- a/drivers/crypto/inside-secure/safexcel.h
+++ b/drivers/crypto/inside-secure/safexcel.h
@@ -306,6 +306,7 @@
#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)

23
target/linux/mediatek/patches-5.4/0502-dts-mt7623-eip97-inside-secure-support.patch Normal file
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@ -0,0 +1,23 @@
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -1047,17 +1047,14 @@
};
crypto: crypto@1b240000 {
- compatible = "mediatek,eip97-crypto";
+ compatible = "inside-secure,safexcel-eip97";
reg = <0 0x1b240000 0 0x20000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
- clock-names = "cryp";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
- status = "disabled";
};
bdpsys: syscon@1c000000 {