From 12584395dc5d45333df298554ff73a8b9495e119 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Sat, 2 Sep 2023 00:18:18 +0200 Subject: [PATCH] sunxi: add support for H616 SoC and Orangepi Zero 2 Specifications: SoC: Allwinner H616 @ 1.5 Ghz DRAM: 1Gb LPDDR3 Power: 5V USB-C Video: HDMI (Type 2.0A - micro) Network: 10/100/1000Mbps Ethernet (Realtek RTL8211F), AW859A BT+wifi Storage: microSD / 2Mb SPI flash USB: 1 USB2.0 Host Debug Serial UART Flashing instructions: Standard sunxi SD card installation procedure - copy image to SD card, insert into SD card slot on the device and boot. Signed-off-by: Zoltan HERPAI --- .../boot/arm-trusted-firmware-sunxi/Makefile | 8 +- package/boot/uboot-sunxi/Makefile | 10 + package/boot/uboot-sunxi/uEnv-h616.txt | 7 + target/linux/sunxi/cortexa53/config-6.1 | 4 +- target/linux/sunxi/image/cortexa53.mk | 12 ++ ...dings-usb-Add-H616-compatible-string.patch | 43 ++++ ...Add-special-clock-for-Allwinner-H616.patch | 82 ++++++++ ...m64-dts-allwinner-h616-Add-USB-nodes.patch | 190 ++++++++++++++++++ ...ner-h616-OrangePi-Zero-2-Add-USB-nod.patch | 84 ++++++++ 9 files changed, 438 insertions(+), 2 deletions(-) create mode 100644 package/boot/uboot-sunxi/uEnv-h616.txt create mode 100644 target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch create mode 100644 target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch create mode 100644 target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch create mode 100644 target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch diff --git a/package/boot/arm-trusted-firmware-sunxi/Makefile b/package/boot/arm-trusted-firmware-sunxi/Makefile index 0535640f95..c9d5668122 100644 --- a/package/boot/arm-trusted-firmware-sunxi/Makefile +++ b/package/boot/arm-trusted-firmware-sunxi/Makefile @@ -36,9 +36,15 @@ define Trusted-Firmware-A/sunxi-h6 PLAT:=sun50i_h6 endef +define Trusted-Firmware-A/sunxi-h616 + NAME:=Allwinner H616 + PLAT:=sun50i_h616 +endef + TFA_TARGETS:= \ sunxi-a64 \ - sunxi-h6 + sunxi-h6 \ + sunxi-h616 define Package/trusted-firmware-a/install $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/package/boot/uboot-sunxi/Makefile b/package/boot/uboot-sunxi/Makefile index be4c8411a9..e141eb7af7 100644 --- a/package/boot/uboot-sunxi/Makefile +++ b/package/boot/uboot-sunxi/Makefile @@ -328,6 +328,15 @@ define U-Boot/orangepi_pc2 ATF:=a64 endef +define U-Boot/orangepi_zero2 + BUILD_SUBTARGET:=cortexa53 + NAME:=Xunlong Orange Pi Zero2 + BUILD_DEVICES:=xunlong_orangepi-zero2 + DEPENDS:=+PACKAGE_u-boot-orangepi_zero2:trusted-firmware-a-sunxi-h616 + UENV:=h616 + ATF:=h616 +endef + define U-Boot/Bananapi_M2_Ultra BUILD_SUBTARGET:=cortexa7 NAME:=Bananapi M2 Ultra @@ -382,6 +391,7 @@ UBOOT_TARGETS := \ orangepi_plus \ orangepi_2 \ orangepi_pc2 \ + orangepi_zero2 \ pangolin \ pine64_plus \ Sinovoip_BPI_M3 \ diff --git a/package/boot/uboot-sunxi/uEnv-h616.txt b/package/boot/uboot-sunxi/uEnv-h616.txt new file mode 100644 index 0000000000..78810ff223 --- /dev/null +++ b/package/boot/uboot-sunxi/uEnv-h616.txt @@ -0,0 +1,7 @@ +setenv mmc_rootpart 2 +part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid +setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage +setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb +setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait +setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r +run uenvcmd diff --git a/target/linux/sunxi/cortexa53/config-6.1 b/target/linux/sunxi/cortexa53/config-6.1 index 54453d75ec..f57c664540 100644 --- a/target/linux/sunxi/cortexa53/config-6.1 +++ b/target/linux/sunxi/cortexa53/config-6.1 @@ -66,6 +66,8 @@ CONFIG_PINCTRL_SUN50I_A64_R=y CONFIG_PINCTRL_SUN50I_H5=y CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y # CONFIG_PREEMPT_DYNAMIC is not set CONFIG_QUEUED_RWLOCKS=y CONFIG_QUEUED_SPINLOCKS=y @@ -83,7 +85,7 @@ CONFIG_SUN50I_A100_R_CCU=y CONFIG_SUN50I_A64_CCU=y CONFIG_SUN50I_DE2_BUS=y CONFIG_SUN50I_ERRATUM_UNKNOWN1=y -# CONFIG_SUN50I_H616_CCU is not set +CONFIG_SUN50I_H616_CCU=y CONFIG_SUN50I_H6_CCU=y CONFIG_SUN50I_H6_R_CCU=y # CONFIG_SUN6I_RTC_CCU is not set diff --git a/target/linux/sunxi/image/cortexa53.mk b/target/linux/sunxi/image/cortexa53.mk index a00bac2c81..80718b34bf 100644 --- a/target/linux/sunxi/image/cortexa53.mk +++ b/target/linux/sunxi/image/cortexa53.mk @@ -24,6 +24,11 @@ define Device/sun50i-h6 $(Device/sun50i) endef +define Device/sun50i-h616 + SOC := sun50i-h616 + $(Device/sun50i) +endef + define Device/friendlyarm_nanopi-neo-plus2 DEVICE_VENDOR := FriendlyARM DEVICE_MODEL := NanoPi NEO Plus2 @@ -108,6 +113,13 @@ define Device/xunlong_orangepi-pc2 endef TARGET_DEVICES += xunlong_orangepi-pc2 +define Device/xunlong_orangepi-zero2 + DEVICE_VENDOR := Xunlong + DEVICE_MODEL := Orange Pi Zero 2 + $(Device/sun50i-h616) +endef +TARGET_DEVICES += xunlong_orangepi-zero2 + define Device/xunlong_orangepi-zero-plus DEVICE_VENDOR := Xunlong DEVICE_MODEL := Orange Pi Zero Plus diff --git a/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch new file mode 100644 index 0000000000..929b567e67 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/460-dt-bindings-usb-Add-H616-compatible-string.patch @@ -0,0 +1,43 @@ +From e4045c8125d88a9eb8b4f8f74b5c7955d5d9adc0 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Thu, 17 Jun 2021 10:54:22 +0100 +Subject: [PATCH 5000/5006] dt-bindings: usb: Add H616 compatible string + +The Allwinner H616 contains four fully OHCI/EHCI compatible USB host +controllers, so just add their compatible strings to the list of +generic OHCI/EHCI controllers. + +Signed-off-by: Andre Przywara +Acked-by: Krzysztof Kozlowski +--- + Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + + Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml +index c5f629c5bc61..994818cb6044 100644 +--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml ++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml +@@ -30,6 +30,7 @@ properties: + - allwinner,sun4i-a10-ehci + - allwinner,sun50i-a64-ehci + - allwinner,sun50i-h6-ehci ++ - allwinner,sun50i-h616-ehci + - allwinner,sun5i-a13-ehci + - allwinner,sun6i-a31-ehci + - allwinner,sun7i-a20-ehci +diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml +index f838f78d6164..4fcbd0add49d 100644 +--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml ++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml +@@ -20,6 +20,7 @@ properties: + - allwinner,sun4i-a10-ohci + - allwinner,sun50i-a64-ohci + - allwinner,sun50i-h6-ohci ++ - allwinner,sun50i-h616-ohci + - allwinner,sun5i-a13-ohci + - allwinner,sun6i-a31-ohci + - allwinner,sun7i-a20-ohci +-- +2.20.1 + diff --git a/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch b/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch new file mode 100644 index 0000000000..2cd3acce2c --- /dev/null +++ b/target/linux/sunxi/patches-6.1/461-dt-bindings-phy-Add-special-clock-for-Allwinner-H616.patch @@ -0,0 +1,82 @@ +From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Mon, 12 Sep 2022 00:03:22 +0100 +Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner + H616 PHY + +The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves +some resources from port 2's PHY and HCI IP. In particular the PMU clock +for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL +register of port 2. To allow each USB port to be controlled +independently of port 2, we need a handle to that particular PMU clock +in the *PHY* node, as the HCI and PHY part might be handled by separate +drivers. + +Add that clock to the requirements of the H616 PHY binding, so that a +PHY driver can apply the quirk in isolation, without requiring help from +port 2's HCI driver. + +Signed-off-by: Andre Przywara +--- + .../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +index 77539b4601c2..2df012d13655 100644 +--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +@@ -36,18 +36,22 @@ properties: + - const: pmu3 + + clocks: ++ minItems: 4 + items: + - description: USB OTG PHY bus clock + - description: USB Host 0 PHY bus clock + - description: USB Host 1 PHY bus clock + - description: USB Host 2 PHY bus clock ++ - description: PMU clock for host port 2 + + clock-names: ++ minItems: 4 + items: + - const: usb0_phy + - const: usb1_phy + - const: usb2_phy + - const: usb3_phy ++ - const: pmu2_clk + + resets: + items: +@@ -96,6 +100,28 @@ required: + - resets + - reset-names + ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - allwinner,sun50i-h616-usb-phy ++ then: ++ properties: ++ clocks: ++ minItems: 5 ++ ++ clock-names: ++ minItems: 5 ++ else: ++ properties: ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ maxItems: 4 ++ + additionalProperties: false + + examples: +-- +2.20.1 + diff --git a/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch b/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch new file mode 100644 index 0000000000..5d626a014e --- /dev/null +++ b/target/linux/sunxi/patches-6.1/462-arm64-dts-allwinner-h616-Add-USB-nodes.patch @@ -0,0 +1,190 @@ +From 4cfd9d9350a57fc3ced240dbf61ca2f444283c50 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Wed, 16 Jun 2021 18:20:47 +0100 +Subject: [PATCH 5004/5006] arm64: dts: allwinner: h616: Add USB nodes + +Add the nodes for the MUSB and the four USB host controllers to the SoC +.dtsi, along with the PHY node needed to bind all of them together. + +EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires +some quirks (handled in the driver). + +Signed-off-by: Andre Przywara +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++ + 1 file changed, 160 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 622a1f7d1641..74aed0d232a9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -504,6 +504,166 @@ + }; + }; + ++ usbotg: usb@5100000 { ++ compatible = "allwinner,sun50i-h616-musb", ++ "allwinner,sun8i-h3-musb"; ++ reg = <0x05100000 0x0400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = ; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ status = "disabled"; ++ }; ++ ++ usbphy: phy@5100400 { ++ compatible = "allwinner,sun50i-h616-usb-phy"; ++ reg = <0x05100400 0x24>, ++ <0x05101800 0x14>, ++ <0x05200800 0x14>, ++ <0x05310800 0x14>, ++ <0x05311800 0x14>; ++ reg-names = "phy_ctrl", ++ "pmu0", ++ "pmu1", ++ "pmu2", ++ "pmu3"; ++ clocks = <&ccu CLK_USB_PHY0>, ++ <&ccu CLK_USB_PHY1>, ++ <&ccu CLK_USB_PHY2>, ++ <&ccu CLK_USB_PHY3>, ++ <&ccu CLK_BUS_EHCI2>; ++ clock-names = "usb0_phy", ++ "usb1_phy", ++ "usb2_phy", ++ "usb3_phy", ++ "pmu2_clk"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY1>, ++ <&ccu RST_USB_PHY2>, ++ <&ccu RST_USB_PHY3>; ++ reset-names = "usb0_reset", ++ "usb1_reset", ++ "usb2_reset", ++ "usb3_reset"; ++ status = "disabled"; ++ #phy-cells = <1>; ++ }; ++ ++ ehci0: usb@5101000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05101000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_BUS_EHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>, ++ <&ccu RST_BUS_EHCI0>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@5101400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05101400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci1: usb@5200000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05200000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_BUS_EHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>, ++ <&ccu RST_BUS_EHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci1: usb@5200400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05200400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci2: usb@5310000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05310000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI2>, ++ <&ccu CLK_BUS_EHCI2>, ++ <&ccu CLK_USB_OHCI2>; ++ resets = <&ccu RST_BUS_OHCI2>, ++ <&ccu RST_BUS_EHCI2>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci2: usb@5310400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05310400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI2>, ++ <&ccu CLK_USB_OHCI2>; ++ resets = <&ccu RST_BUS_OHCI2>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ehci3: usb@5311000 { ++ compatible = "allwinner,sun50i-h616-ehci", ++ "generic-ehci"; ++ reg = <0x05311000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_BUS_EHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>, ++ <&ccu RST_BUS_EHCI3>; ++ phys = <&usbphy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci3: usb@5311400 { ++ compatible = "allwinner,sun50i-h616-ohci", ++ "generic-ohci"; ++ reg = <0x05311400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>; ++ phys = <&usbphy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h616-rtc"; + reg = <0x07000000 0x400>; +-- +2.20.1 + diff --git a/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch b/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch new file mode 100644 index 0000000000..d3460c54e6 --- /dev/null +++ b/target/linux/sunxi/patches-6.1/463-arm64-dts-allwinner-h616-OrangePi-Zero-2-Add-USB-nod.patch @@ -0,0 +1,84 @@ +From 1bc12a9ae690a22a525f9b71778022bb4533fec1 Mon Sep 17 00:00:00 2001 +From: Andre Przywara +Date: Wed, 16 Jun 2021 18:32:36 +0100 +Subject: [PATCH 5005/5006] arm64: dts: allwinner: h616: OrangePi Zero 2: Add + USB nodes + +The OrangePi Zero 2 has one USB-A host port, VBUS is provided by +a GPIO controlled regulator. +The USB-C port is meant to power the board, but is also connected to +the USB 0 port, which we configure as an MUSB peripheral. + +Signed-off-by: Andre Przywara +--- + .../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++ + 1 file changed, 41 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +index 02893f3ac99d..cb8600d0ea1e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +@@ -49,8 +49,24 @@ + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; ++ ++ reg_usb1_vbus: regulator-usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v>; ++ enable-active-high; ++ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ ++ }; + }; + ++&ehci1 { ++ status = "okay"; ++}; ++ ++/* USB 2 & 3 are on headers only. */ ++ + &emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; +@@ -76,6 +92,10 @@ + status = "okay"; + }; + ++&ohci1 { ++ status = "okay"; ++}; ++ + &r_rsb { + status = "okay"; + +@@ -211,3 +231,24 @@ + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; + }; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_usb1_vbus>; ++ status = "okay"; ++}; +-- +2.20.1 +