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rtl838x: Add support for RTL839x internal PHY
This adds basic support for reading the internal PHYs of the RTL839x SoCs and full support for the 2 PHYs connected to the 1000Base-X SerDes of the RTL8393 SoC. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
John Crispin
parent
3c4063f715
commit
121ef9ddc9
@ -38,6 +38,14 @@
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#define RTL838X_STAT_CTRL (0x3108)
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#define RTL839X_STAT_CTRL (0x04cc)
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/* Registers of the internal Serdes of the 8390 */
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#define RTL8390_SDS0_1_XSG0 (0xA000)
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#define RTL8390_SDS0_1_XSG1 (0xA100)
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#define RTL839X_SDS12_13_XSG0 (0xB800)
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#define RTL839X_SDS12_13_XSG1 (0xB900)
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#define RTL839X_SDS12_13_PWR0 (0xb880)
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#define RTL839X_SDS12_13_PWR1 (0xb980)
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/* Registers of the internal Serdes of the 8380 */
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#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28
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#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100)
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@ -23,6 +23,7 @@
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#define PHY_ID_RTL8218B_E 0x001cc981
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#define PHY_ID_RTL8218B_I 0x001cca40
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#define PHY_ID_RTL8390_GENERIC 0x001ccab0
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#define PHY_ID_RTL8393_I 0x001c8393
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struct __attribute__ ((__packed__)) part {
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uint16_t start;
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@ -118,6 +119,116 @@ void rtl8380_sds_rst(int mac)
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pr_info("SERDES reset: %d\n", mac);
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}
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int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
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{
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int offset = 0;
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int reg;
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u32 val;
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if (phy_addr == 49)
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offset = 0x100;
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/* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
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* which would otherwise read as 0
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*/
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if (soc_info.id == 0x8393) {
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if (phy_reg == 2)
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return 0x1c;
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if (phy_reg == 3)
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return 0x8393;
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}
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reg = (phy_reg << 1) & 0xfc;
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val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
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if (phy_reg & 1)
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val = (val >> 16) & 0xffff;
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else
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val &= 0xffff;
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return val;
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}
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int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
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{
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int offset = 0;
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u32 val;
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if (phy_addr == 26)
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offset = 0x100;
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val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
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return val;
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}
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int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
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{
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int offset = 0;
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int reg;
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u32 val;
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if (phy_addr == 49)
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offset = 0x100;
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reg = (phy_reg << 1) & 0xfc;
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val = v;
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if (phy_reg & 1) {
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val = val << 16;
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sw_w32_mask(0xffff0000, val,
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RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
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} else {
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sw_w32_mask(0xffff, val,
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RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
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}
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return 0;
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}
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/* Read the link and speed status of the 2 internal SGMII/1000Base-X
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* ports of the RTL838x SoCs
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*/
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static int rtl8380_read_status(struct phy_device *phydev)
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{
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int err;
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int phy_addr = phydev->mdio.addr;
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err = genphy_read_status(phydev);
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if (phydev->link) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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return err;
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}
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/* Read the link and speed status of the 2 internal SGMII/1000Base-X
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* ports of the RTL8393 SoC
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*/
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static int rtl8393_read_status(struct phy_device *phydev)
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{
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int offset = 0;
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int err;
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int phy_addr = phydev->mdio.addr;
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u32 v;
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err = genphy_read_status(phydev);
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if (phy_addr == 49)
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offset = 0x100;
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if (phydev->link) {
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phydev->speed = SPEED_100;
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/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
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* PHY registers
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*/
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v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
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if (!(v & (1 << 13)) && (v & (1 << 6)))
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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return err;
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}
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static struct fw_header *
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rtl838x_request_fw(struct phy_device *phydev, const struct firmware *fw,
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const char *name)
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@ -406,7 +517,15 @@ static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
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{
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int addr = phydev->mdio.addr;
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return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
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/* Both the RTL8214FC and the external RTL8218B have the same
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* PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
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* at PHY IDs 0-7, while the RTL8214FC must be attached via
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* the pair of SGMII/1000Base-X with higher PHY-IDs
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*/
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if (soc_info.family == RTL8380_FAMILY_ID)
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return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
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else
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return phydev->phy_id == PHY_ID_RTL8218B_E;
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}
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@ -1065,12 +1184,32 @@ static int rtl8380_configure_serdes(struct phy_device *phydev)
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return 0;
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}
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static int rtl8390_configure_serdes(struct phy_device *phydev)
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{
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phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
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/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
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sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
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/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
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* FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
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* and FRE16_EEE_QUIET_FIB1G
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*/
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sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
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return 0;
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}
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static int rtl8214fc_phy_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct rtl838x_phy_priv *priv;
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int addr = phydev->mdio.addr;
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/* 839x has internal SerDes */
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if (soc_info.id == 0x8393)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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@ -1118,7 +1257,7 @@ static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
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priv->name = "RTL8218B (external)";
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/* All base addresses of the PHYs start at multiples of 8 */
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if (!(addr % 8)) {
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if (!(addr % 8) && soc_info.family == RTL8380_FAMILY_ID) {
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/* Configuration must be done while patching still possible */
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return rtl8380_configure_ext_rtl8218b(phydev);
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}
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@ -1176,6 +1315,27 @@ static int rtl838x_serdes_probe(struct phy_device *phydev)
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return -ENODEV;
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}
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static int rtl8393_serdes_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct rtl838x_phy_priv *priv;
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int addr = phydev->mdio.addr;
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pr_info("%s: id: %d\n", __func__, addr);
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if (soc_info.family != RTL8390_FAMILY_ID)
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return -ENODEV;
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if (addr < 24)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->name = "RTL8393 Serdes";
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return rtl8390_configure_serdes(phydev);
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}
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static int rtl8390_serdes_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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@ -1198,8 +1358,8 @@ static int rtl8390_serdes_probe(struct phy_device *phydev)
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static struct phy_driver rtl838x_phy_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
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.name = "REATLTEK RTL8214C",
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
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.name = "REALTEK RTL8214C",
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.features = PHY_GBIT_FEATURES,
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.match_phy_device = rtl8214c_match_phy_device,
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.probe = rtl8214c_phy_probe,
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@ -1209,7 +1369,7 @@ static struct phy_driver rtl838x_phy_driver[] = {
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
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.name = "REATLTEK RTL8214FC",
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.name = "REALTEK RTL8214FC",
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.features = PHY_GBIT_FIBRE_FEATURES,
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.match_phy_device = rtl8214fc_match_phy_device,
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.probe = rtl8214fc_phy_probe,
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@ -1225,7 +1385,7 @@ static struct phy_driver rtl838x_phy_driver[] = {
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
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.name = "REATLTEK RTL8218B (external)",
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.name = "REALTEK RTL8218B (external)",
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.features = PHY_GBIT_FEATURES,
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.match_phy_device = rtl8218b_ext_match_phy_device,
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.probe = rtl8218b_ext_phy_probe,
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@ -1239,7 +1399,7 @@ static struct phy_driver rtl838x_phy_driver[] = {
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
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.name = "REATLTEK RTL8218B (internal)",
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.name = "REALTEK RTL8218B (internal)",
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.features = PHY_GBIT_FEATURES,
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.probe = rtl8218b_int_phy_probe,
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.suspend = genphy_suspend,
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@ -1252,7 +1412,7 @@ static struct phy_driver rtl838x_phy_driver[] = {
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
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.name = "REATLTEK RTL8380 SERDES",
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.name = "REALTEK RTL8380 SERDES",
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.features = PHY_GBIT_FIBRE_FEATURES,
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.probe = rtl838x_serdes_probe,
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.suspend = genphy_suspend,
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@ -1260,10 +1420,21 @@ static struct phy_driver rtl838x_phy_driver[] = {
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.set_loopback = genphy_loopback,
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.read_mmd = rtl8380_rtl8218b_read_mmd,
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.write_mmd = rtl8380_rtl8218b_write_mmd,
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.read_status = rtl8380_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
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.name = "REALTEK RTL8393 SERDES",
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.features = PHY_GBIT_FIBRE_FEATURES,
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.probe = rtl8393_serdes_probe,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.set_loopback = genphy_loopback,
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.read_status = rtl8393_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
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.name = "REATLTEK RTL8390 Generic",
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.name = "REALTEK RTL8390 Generic",
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.features = PHY_GBIT_FIBRE_FEATURES,
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.probe = rtl8390_serdes_probe,
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.suspend = genphy_suspend,
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