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ag71xx: add F1E specific feature bit definitions to AR934X register file

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The F1E Phy (AR8035?) requires additional bits to be
set in order to provide a fast and reliable connection
over gigabit links.

When enabled, the link doesn't suffer anymore from a small
package loss under load and the performance is improved
quite a bit as well. (203 mbit/s vs 112 mbit/s, iperf tcp).

Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Patchwork: http://patchwork.openwrt.org/patch/4460/
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 38948
This commit is contained in:
Gabor Juhos 2013-11-29 20:18:43 +00:00
parent cad5257732
commit 1167f92ac6
1 changed files with 3 additions and 1 deletions
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4
target/linux/ar71xx/patches-3.10/601-MIPS-ath79-add-more-register-defines.patch
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@ -207,7 +207,7 @@
#define AR934X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
@@ -561,4 +664,144 @@
@@ -561,4 +664,146 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@ -341,6 +341,8 @@
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+
+/*
+ * QCA955X GMAC Interface