uboot-rockchip: add ArmSoM Sige7 support
Add support for the ArmSoM Sige7 board. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16462 Signed-off-by: Nick Hainke <vincent@systemli.org>
This commit is contained in:
Tianling Shen
Nick Hainke
parent
e05b24175d
commit
0c1332d034
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@ -259,6 +259,13 @@ define U-Boot/rock5b-rk3588
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radxa_rock-5b
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endef
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define U-Boot/sige7-rk3588
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$(U-Boot/rk3588/Default)
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NAME:=Sige7
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BUILD_DEVICES:= \
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armsom_sige7
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endef
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# RK3588S boards
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@ -309,6 +316,7 @@ UBOOT_TARGETS := \
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rock-3b-rk3568 \
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nanopc-t6-rk3588 \
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rock5b-rk3588 \
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sige7-rk3588 \
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nanopi-r6c-rk3588s \
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nanopi-r6s-rk3588s \
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rock5a-rk3588s
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@ -10,6 +10,700 @@ Subject: [PATCH] Squashed 'dts/upstream/' changes from
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6s.dts
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--- /dev/null
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+++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts
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@@ -0,0 +1,691 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+#include "rk3588.dtsi"
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+
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+/ {
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+ model = "ArmSoM Sige7";
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+ compatible = "armsom,sige7", "rockchip,rk3588";
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+
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+ aliases {
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+ mmc0 = &sdhci;
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+ mmc1 = &sdmmc;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ analog-sound {
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+ compatible = "audio-graph-card";
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+ dais = <&i2s0_8ch_p0>;
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+ label = "rk3588-es8316";
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+ hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hp_detect>;
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+ routing = "MIC2", "Mic Jack",
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+ "Headphones", "HPOL",
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+ "Headphones", "HPOR";
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+ widgets = "Microphone", "Mic Jack",
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+ "Headphone", "Headphones";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&led_rgb_g>;
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+
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+ led_green: led-0 {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+
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+ led_red: led-1 {
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+ color = <LED_COLOR_ID_RED>;
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "none";
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+ };
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+ };
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+
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+ fan: pwm-fan {
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+ compatible = "pwm-fan";
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+ cooling-levels = <0 95 145 195 255>;
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+ fan-supply = <&vcc5v0_sys>;
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+ pwms = <&pwm1 0 50000 0>;
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+ #cooling-cells = <2>;
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+ };
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+
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+ vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_pcie2x1l2";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc_3v3_s3>;
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+ };
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+
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+ vcc3v3_pcie30: vcc3v3-pcie30-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
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+ regulator-name = "vcc3v3_pcie30";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <5000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc5v0_host: vcc5v0-host-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_host";
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ enable-active-high;
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+ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc5v0_host_en>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+
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+ vcc5v0_sys: vcc5v0-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_1v1_nldo_s3";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ vin-supply = <&vcc5v0_sys>;
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+ };
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+};
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+
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+&combphy0_ps {
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+ status = "okay";
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+};
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+
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+&combphy1_ps {
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+ status = "okay";
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+};
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+
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+&combphy2_psu {
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+ status = "okay";
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+};
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+
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+&cpu_b0 {
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+ cpu-supply = <&vdd_cpu_big0_s0>;
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+};
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+
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+&cpu_b1 {
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+ cpu-supply = <&vdd_cpu_big0_s0>;
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+};
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+
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+&cpu_b2 {
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+ cpu-supply = <&vdd_cpu_big1_s0>;
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+};
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+
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+&cpu_b3 {
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+ cpu-supply = <&vdd_cpu_big1_s0>;
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+};
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+
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+&cpu_l0 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l1 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l2 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&cpu_l3 {
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+ cpu-supply = <&vdd_cpu_lit_s0>;
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+};
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+
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+&i2c0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c0m2_xfer>;
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+ status = "okay";
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+
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+ vdd_cpu_big0_s0: regulator@42 {
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+ compatible = "rockchip,rk8602";
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+ reg = <0x42>;
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+ fcs,suspend-voltage-selector = <1>;
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+ regulator-name = "vdd_cpu_big0_s0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <550000>;
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+ regulator-max-microvolt = <1050000>;
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+ regulator-ramp-delay = <2300>;
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+ vin-supply = <&vcc5v0_sys>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_cpu_big1_s0: regulator@43 {
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+ compatible = "rockchip,rk8603", "rockchip,rk8602";
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+ reg = <0x43>;
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+ fcs,suspend-voltage-selector = <1>;
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+ regulator-name = "vdd_cpu_big1_s0";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <550000>;
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+ regulator-max-microvolt = <1050000>;
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+ regulator-ramp-delay = <2300>;
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+ vin-supply = <&vcc5v0_sys>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+};
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+
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+&i2c6 {
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+ status = "okay";
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+
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+ hym8563: rtc@51 {
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+ compatible = "haoyu,hym8563";
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+ reg = <0x51>;
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <0>;
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+ clock-output-names = "hym8563";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&hym8563_int>;
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+ wakeup-source;
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+ };
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+};
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+
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+&i2c7 {
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+ status = "okay";
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+
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+ es8316: audio-codec@11 {
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+ compatible = "everest,es8316";
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+ reg = <0x11>;
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+ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
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+ assigned-clock-rates = <12288000>;
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+ clocks = <&cru I2S0_8CH_MCLKOUT>;
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+ clock-names = "mclk";
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+ #sound-dai-cells = <0>;
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+
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+ port {
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+ es8316_p0_0: endpoint {
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+ remote-endpoint = <&i2s0_8ch_p0_0>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2s0_8ch {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2s0_lrck
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+ &i2s0_mclk
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+ &i2s0_sclk
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+ &i2s0_sdi0
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+ &i2s0_sdo0>;
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+ status = "okay";
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+
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+ i2s0_8ch_p0: port {
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+ i2s0_8ch_p0_0: endpoint {
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+ dai-format = "i2s";
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+ mclk-fs = <256>;
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+ remote-endpoint = <&es8316_p0_0>;
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+ };
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+ };
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+};
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+
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+/* phy1 - right ethernet port */
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+&pcie2x1l0 {
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+ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+};
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+
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+/* phy2 - WiFi */
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+&pcie2x1l1 {
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+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+};
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+
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+/* phy0 - left ethernet port */
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+&pcie2x1l2 {
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+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
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+ status = "okay";
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+};
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+
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+&pcie30phy {
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+ status = "okay";
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+};
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+
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+&pcie3x4 {
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+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
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+ vpcie3v3-supply = <&vcc3v3_pcie30>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ hym8563 {
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+ hym8563_int: hym8563-int {
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+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ leds {
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+ led_rgb_g: led-rgb-g {
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+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ led_rgb_r: led-rgb-r {
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+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ sound {
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+ hp_detect: hp-detect {
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+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ usb {
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+ vcc5v0_host_en: vcc5v0-host-en {
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+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+};
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+
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+&pwm1 {
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+ status = "okay";
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+};
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+
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+&saradc {
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+ vref-supply = <&avcc_1v8_s0>;
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+ status = "okay";
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+};
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+
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+&sdhci {
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+ bus-width = <8>;
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+ no-sdio;
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+ no-sd;
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+ non-removable;
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+ mmc-hs200-1_8v;
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+ status = "okay";
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+};
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+
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+&sdmmc {
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+ bus-width = <4>;
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+ cap-mmc-highspeed;
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+ cap-sd-highspeed;
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+ disable-wp;
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+ max-frequency = <200000000>;
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+ no-sdio;
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+ no-mmc;
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+ sd-uhs-sdr104;
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+ vmmc-supply = <&vcc_3v3_s3>;
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+ vqmmc-supply = <&vccio_sd_s0>;
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+ status = "okay";
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+};
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+
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+&spi2 {
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+ assigned-clocks = <&cru CLK_SPI2>;
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+ assigned-clock-rates = <200000000>;
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+ num-cs = <1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
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+ status = "okay";
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+
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+ pmic@0 {
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+ compatible = "rockchip,rk806";
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+ spi-max-frequency = <1000000>;
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+ reg = <0x0>;
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+
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
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+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
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+
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+ system-power-controller;
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+
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+ vcc1-supply = <&vcc5v0_sys>;
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+ vcc2-supply = <&vcc5v0_sys>;
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+ vcc3-supply = <&vcc5v0_sys>;
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+ vcc4-supply = <&vcc5v0_sys>;
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+ vcc5-supply = <&vcc5v0_sys>;
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+ vcc6-supply = <&vcc5v0_sys>;
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+ vcc7-supply = <&vcc5v0_sys>;
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+ vcc8-supply = <&vcc5v0_sys>;
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+ vcc9-supply = <&vcc5v0_sys>;
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+ vcc10-supply = <&vcc5v0_sys>;
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+ vcc11-supply = <&vcc_2v0_pldo_s3>;
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+ vcc12-supply = <&vcc5v0_sys>;
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+ vcc13-supply = <&vcc_1v1_nldo_s3>;
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+ vcc14-supply = <&vcc_1v1_nldo_s3>;
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+ vcca-supply = <&vcc5v0_sys>;
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+
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+ rk806_dvs1_null: dvs1-null-pins {
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+ pins = "gpio_pwrctrl1";
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+ function = "pin_fun0";
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+ };
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+
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+ rk806_dvs2_null: dvs2-null-pins {
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+ pins = "gpio_pwrctrl2";
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+ function = "pin_fun0";
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+ };
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+
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+ rk806_dvs3_null: dvs3-null-pins {
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+ pins = "gpio_pwrctrl3";
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+ function = "pin_fun0";
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+ };
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+
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+ regulators {
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+ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <550000>;
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+ regulator-max-microvolt = <950000>;
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+ regulator-ramp-delay = <12500>;
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+ regulator-name = "vdd_gpu_s0";
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+ regulator-enable-ramp-delay = <400>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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||||
+ };
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||||
+ };
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+
|
||||
+ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_cpu_lit_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_log_s0: dcdc-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <675000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_log_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <750000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <550000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_vdenc_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_ddr_s0: dcdc-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <675000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_ddr_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <850000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd2_ddr_s3: dcdc-reg6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vdd2_ddr_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_2v0_pldo_s3: dcdc-reg7 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2000000>;
|
||||
+ regulator-max-microvolt = <2000000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vdd_2v0_pldo_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <2000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_s3: dcdc-reg8 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-name = "vcc_3v3_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vddq_ddr_s0: dcdc-reg9 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-name = "vddq_ddr_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_s3: dcdc-reg10 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avcc_1v8_s0: pldo-reg1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "avcc_1v8_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_s0: pldo-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "vcc_1v8_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_1v2_s0: pldo-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1200000>;
|
||||
+ regulator-max-microvolt = <1200000>;
|
||||
+ regulator-name = "avdd_1v2_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3_s0: pldo-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vcc_3v3_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd_s0: pldo-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+ regulator-name = "vccio_sd_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pldo6_s3: pldo-reg6 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-name = "pldo6_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_0v75_s3: nldo-reg1 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "vdd_0v75_s3";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <750000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_ddr_pll_s0: nldo-reg2 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <850000>;
|
||||
+ regulator-max-microvolt = <850000>;
|
||||
+ regulator-name = "vdd_ddr_pll_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <850000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ avdd_0v75_s0: nldo-reg3 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "avdd_0v75_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_0v85_s0: nldo-reg4 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <850000>;
|
||||
+ regulator-max-microvolt = <850000>;
|
||||
+ regulator-name = "vdd_0v85_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_0v75_s0: nldo-reg5 {
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <750000>;
|
||||
+ regulator-max-microvolt = <750000>;
|
||||
+ regulator-name = "vdd_0v75_s0";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&u2phy3 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy3_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ pinctrl-0 = <&uart2m0_xfer>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6c.dts
|
||||
@@ -0,0 +1,14 @@
|
||||
|
|
|
|||
|
|
@ -0,0 +1,257 @@
|
|||
From 40b573e4f6ed629eab54633f8836a2be5e5aa75a Mon Sep 17 00:00:00 2001
|
||||
From: Jianfeng Liu <liujianfeng1994@gmail.com>
|
||||
Date: Wed, 29 May 2024 01:04:06 +0800
|
||||
Subject: [PATCH] board: rockchip: add ArmSoM Sige7 Rk3588 board
|
||||
|
||||
ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer) by
|
||||
ArmSoM.
|
||||
|
||||
There are two variants depending on the DRAM size : 8G and 16G.
|
||||
|
||||
Specification:
|
||||
|
||||
Rockchip Rk3588 SoC
|
||||
4x ARM Cortex-A76, 4x ARM Cortex-A55
|
||||
8/16GB memory LPDDR4x
|
||||
Mali G610MC4 GPU
|
||||
2x MIPI CSI 2 multiple lanes connector
|
||||
64GB/128GB on board eMMC
|
||||
uSD slot
|
||||
1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
|
||||
1x HDMI 2.1 output
|
||||
2x 2.5 Gbps Ethernet port
|
||||
40-pin IO header including UART, SPI and I2C
|
||||
USB PD over USB Type-C
|
||||
Size: 92mm x 62mm
|
||||
|
||||
Kernel commit:
|
||||
81c828a67c78 (arm64: dts: rockchip: Add ArmSom Sige7 board)
|
||||
|
||||
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
|
||||
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
||||
---
|
||||
MAINTAINERS | 1 +
|
||||
arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi | 6 ++
|
||||
arch/arm/mach-rockchip/rk3588/Kconfig | 26 ++++++
|
||||
board/armsom/sige7-rk3588/Kconfig | 12 +++
|
||||
board/armsom/sige7-rk3588/MAINTAINERS | 7 ++
|
||||
configs/sige7-rk3588_defconfig | 93 ++++++++++++++++++++
|
||||
doc/board/rockchip/rockchip.rst | 1 +
|
||||
include/configs/sige7-rk3588.h | 15 ++++
|
||||
8 files changed, 161 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
|
||||
create mode 100644 board/armsom/sige7-rk3588/Kconfig
|
||||
create mode 100644 board/armsom/sige7-rk3588/MAINTAINERS
|
||||
create mode 100644 configs/sige7-rk3588_defconfig
|
||||
create mode 100644 include/configs/sige7-rk3588.h
|
||||
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -533,6 +533,7 @@ F: arch/arm/include/asm/arch-rockchip/
|
||||
F: arch/arm/mach-rockchip/
|
||||
F: board/amarula/vyasa-rk3288/
|
||||
F: board/anbernic/rgxx3_rk3566/
|
||||
+F: board/armsom/sige7-rk3588/
|
||||
F: board/chipspark/popmetal_rk3288
|
||||
F: board/engicam/px30_core/
|
||||
F: board/firefly/
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3588-armsom-sige7-u-boot.dtsi
|
||||
@@ -0,0 +1,6 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include "rk3588-u-boot.dtsi"
|
||||
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
|
||||
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
|
||||
@@ -185,6 +185,31 @@ config TARGET_ROCK5B_RK3588
|
||||
USB PD over USB Type-C
|
||||
Size: 100mm x 72mm (Pico-ITX form factor)
|
||||
|
||||
+config TARGET_SIGE7_RK3588
|
||||
+ bool "ArmSoM Sige7 RK3588 board"
|
||||
+ select BOARD_LATE_INIT
|
||||
+ help
|
||||
+ ArmSoM Sige7 is a Rockchip RK3588 based SBC (Single Board Computer)
|
||||
+ by ArmSoM.
|
||||
+
|
||||
+ There are two variants depending on the DRAM size : 8G and 16G.
|
||||
+
|
||||
+ Specification:
|
||||
+
|
||||
+ Rockchip Rk3588 SoC
|
||||
+ 4x ARM Cortex-A76, 4x ARM Cortex-A55
|
||||
+ 8/16GB memory LPDDR4x
|
||||
+ Mali G610MC4 GPU
|
||||
+ 2x MIPI CSI 2 multiple lanes connector
|
||||
+ 64GB/128GB on board eMMC
|
||||
+ uSD slot
|
||||
+ 1x USB 2.0 Type-A, 1x USB 3.0 Type-A, 1x USB 3.0 Type-C
|
||||
+ 1x HDMI 2.1 output
|
||||
+ 2x 2.5 Gbps Ethernet port
|
||||
+ 40-pin IO header including UART, SPI and I2C
|
||||
+ USB PD over USB Type-C
|
||||
+ Size: 92mm x 62mm
|
||||
+
|
||||
config TARGET_QUARTZPRO64_RK3588
|
||||
bool "Pine64 QuartzPro64 RK3588 board"
|
||||
select BOARD_LATE_INIT
|
||||
@@ -254,6 +279,7 @@ config ROCKCHIP_COMMON_STACK_ADDR
|
||||
config TEXT_BASE
|
||||
default 0x00a00000
|
||||
|
||||
+source "board/armsom/sige7-rk3588/Kconfig"
|
||||
source "board/edgeble/neural-compute-module-6/Kconfig"
|
||||
source "board/friendlyelec/nanopc-t6-rk3588/Kconfig"
|
||||
source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig"
|
||||
--- /dev/null
|
||||
+++ b/board/armsom/sige7-rk3588/Kconfig
|
||||
@@ -0,0 +1,12 @@
|
||||
+if TARGET_SIGE7_RK3588
|
||||
+
|
||||
+config SYS_BOARD
|
||||
+ default "sige7-rk3588"
|
||||
+
|
||||
+config SYS_VENDOR
|
||||
+ default "armsom"
|
||||
+
|
||||
+config SYS_CONFIG_NAME
|
||||
+ default "sige7-rk3588"
|
||||
+
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/board/armsom/sige7-rk3588/MAINTAINERS
|
||||
@@ -0,0 +1,7 @@
|
||||
+SIGE7-RK3588
|
||||
+M: Jianfeng Liu <liujianfeng1994@gmail.com>
|
||||
+S: Maintained
|
||||
+F: board/armsom/sige7-rk3588
|
||||
+F: include/configs/sige7-rk3588.h
|
||||
+F: configs/sige7-rk3588_defconfig
|
||||
+F: arch/arm/dts/rk3588-armsom-sige7*
|
||||
--- /dev/null
|
||||
+++ b/configs/sige7-rk3588_defconfig
|
||||
@@ -0,0 +1,93 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-armsom-sige7"
|
||||
+CONFIG_ROCKCHIP_RK3588=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_TARGET_SIGE7_RK3588=y
|
||||
+CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SPL_SPI=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_PCI=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_AHCI=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_FIT_SIGNATURE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_PCI=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_ROCKUSB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_AHCI_PCI=y
|
||||
+CONFIG_DWC_AHCI=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_PHYLIB=y
|
||||
+CONFIG_RTL8169=y
|
||||
+CONFIG_NVME_PCI=y
|
||||
+CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_PHY_ROCKCHIP_USBDP=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_SCSI=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||
+CONFIG_USB_HOST_ETHER=y
|
||||
+CONFIG_USB_ETHER_ASIX=y
|
||||
+CONFIG_USB_ETHER_ASIX88179=y
|
||||
+CONFIG_USB_ETHER_LAN75XX=y
|
||||
+CONFIG_USB_ETHER_LAN78XX=y
|
||||
+CONFIG_USB_ETHER_MCS7830=y
|
||||
+CONFIG_USB_ETHER_RTL8152=y
|
||||
+CONFIG_USB_ETHER_SMSC95XX=y
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
+CONFIG_USB_FUNCTION_ROCKUSB=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
--- a/doc/board/rockchip/rockchip.rst
|
||||
+++ b/doc/board/rockchip/rockchip.rst
|
||||
@@ -122,6 +122,7 @@ List of mainline supported Rockchip boar
|
||||
- Radxa ROCK 3B (rock-3b-rk3568)
|
||||
|
||||
* rk3588
|
||||
+ - ArmSoM Sige7 (sige7-rk3588)
|
||||
- Rockchip EVB (evb-rk3588)
|
||||
- Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588)
|
||||
- Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588)
|
||||
--- /dev/null
|
||||
+++ b/include/configs/sige7-rk3588.h
|
||||
@@ -0,0 +1,15 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+/*
|
||||
+ * Copyright (c) 2024 ArmSoM Technology Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#ifndef __SIGE7_RK3588_H
|
||||
+#define __SIGE7_RK3588_H
|
||||
+
|
||||
+#define ROCKCHIP_DEVICE_SETTINGS \
|
||||
+ "stdout=serial,vidconsole\0" \
|
||||
+ "stderr=serial,vidconsole\0"
|
||||
+
|
||||
+#include <configs/rk3588_common.h>
|
||||
+
|
||||
+#endif /* __SIGE7_RK3588_H */
|
||||
Loading…
Reference in New Issue