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ramips: Fix amount of MT7621 pins controlled by spi group

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The PINS conntrolled by the SPI bits in the GPIO_MODE register is always
7 and not 8 for nand mode.

Signed-off-by: Sven Eckelmann <sven@open-mesh.com>

SVN-Revision: 46644
This commit is contained in:
John Crispin 2015-08-17 06:15:44 +00:00
parent 9ed654e389
commit 09851afd33
1 changed files with 1 additions and 1 deletions
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target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
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@ -593,7 +593,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
+static struct rt2880_pmx_func spi_grp[] = {
+ FUNC("spi", 0, 34, 7),
+ FUNC("nand", 2, 34, 8),
+ FUNC("nand", 2, 34, 7),
+};
+static struct rt2880_pmx_func sdhci_grp[] = {
+ FUNC("sdhci", 0, 41, 8),