84 lines
3.1 KiB
Diff
84 lines
3.1 KiB
Diff
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From 5afb722d255335954c6b67470e0d261ea5d5ab7a Mon Sep 17 00:00:00 2001
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From: kFYatek <4499762+kFYatek@users.noreply.github.com>
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Date: Wed, 23 Jun 2021 01:11:26 +0200
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Subject: [PATCH] drm/vc4: Fix timings for interlaced modes
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Increase the number of post-sync blanking lines on odd fields instead of
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decreasing it on even fields. This makes the total number of lines
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properly match the modelines.
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Additionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take
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pixels_per_clock into account, causing some displays to invert the
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fields when driven by bcm2711.
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Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 7 ++++---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------
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2 files changed, 10 insertions(+), 9 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -342,7 +342,8 @@ static void vc4_crtc_config_pv(struct dr
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PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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- VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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+ VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
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+ interlace,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
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PV_VERTA_VSYNC));
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@@ -354,7 +355,7 @@ static void vc4_crtc_config_pv(struct dr
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->crtc_vtotal -
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- mode->crtc_vsync_end - 1,
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+ mode->crtc_vsync_end,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->crtc_vsync_end -
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mode->crtc_vsync_start,
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@@ -374,7 +375,7 @@ static void vc4_crtc_config_pv(struct dr
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PV_VCONTROL_CONTINUOUS |
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(is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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- VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
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+ VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
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PV_VCONTROL_ODD_DELAY));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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} else {
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -735,12 +735,12 @@ static void vc4_hdmi_set_timings(struct
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VC4_HDMI_VERTA_VFP) |
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VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
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u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
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- VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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+ VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
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+ interlaced,
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VC4_HDMI_VERTB_VBP));
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u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->crtc_vtotal -
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- mode->crtc_vsync_end -
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- interlaced,
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+ mode->crtc_vsync_end,
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VC4_HDMI_VERTB_VBP));
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HDMI_WRITE(HDMI_HORZA,
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@@ -781,12 +781,12 @@ static void vc5_hdmi_set_timings(struct
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VC5_HDMI_VERTA_VFP) |
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VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
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u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
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- VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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+ VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
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+ interlaced,
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VC4_HDMI_VERTB_VBP));
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u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->crtc_vtotal -
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- mode->crtc_vsync_end -
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- interlaced,
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+ mode->crtc_vsync_end,
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VC4_HDMI_VERTB_VBP));
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unsigned char gcp;
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bool gcp_en;
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