80 lines
3.0 KiB
Diff
80 lines
3.0 KiB
Diff
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From fe77a92b9018f9a2dbab0e2a600e368d55c667b0 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Tue, 13 Apr 2021 11:55:55 +0200
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Subject: [PATCH] drm/vc4: hdmi: Convert to the new clock request API
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The new clock request API allows us to increase the rate of the HSM
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clock to match our pixel rate requirements while decreasing it when
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we're done, resulting in a better power-efficiency.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 22 +++++++++++++++-------
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drivers/gpu/drm/vc4/vc4_hdmi.h | 3 +++
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2 files changed, 18 insertions(+), 7 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -545,6 +545,9 @@ static void vc4_hdmi_encoder_post_crtc_p
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HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
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+ clk_request_done(vc4_hdmi->bvb_req);
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+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
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+ clk_request_done(vc4_hdmi->hsm_req);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
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@@ -849,9 +852,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
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* pixel clock, but HSM ends up being the limiting factor.
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*/
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hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
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- ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
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- if (ret) {
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- DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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+ vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);
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+ if (IS_ERR(vc4_hdmi->hsm_req)) {
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+ DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req));
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return;
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}
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@@ -863,10 +866,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
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* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
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* at 300MHz.
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*/
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- ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
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- (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
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- if (ret) {
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- DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
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+ vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
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+ (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
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+ if (IS_ERR(vc4_hdmi->bvb_req)) {
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+ DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
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+ clk_request_done(vc4_hdmi->hsm_req);
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+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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return;
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}
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@@ -874,6 +879,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
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ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
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if (ret) {
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DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
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+ clk_request_done(vc4_hdmi->bvb_req);
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+ clk_request_done(vc4_hdmi->hsm_req);
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+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
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clk_disable_unprepare(vc4_hdmi->pixel_clock);
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return;
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}
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
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@@ -172,6 +172,9 @@ struct vc4_hdmi {
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struct reset_control *reset;
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+ struct clk_request *bvb_req;
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+ struct clk_request *hsm_req;
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+
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/* Common debugfs regset */
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struct debugfs_regset32 hdmi_regset;
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struct debugfs_regset32 hd_regset;
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