82 lines
2.6 KiB
Diff
82 lines
2.6 KiB
Diff
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From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Sun, 3 Dec 2023 23:39:14 +0800
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Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
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Add node to support all the QUP UART node controller inside of IPQ6018.
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Some routers use these bus to connect Bluetooth chips.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
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1 file changed, 50 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -458,6 +458,26 @@
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qcom,ee = <0>;
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};
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+ blsp1_uart1: serial@78af000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x0 0x78af000 0x0 0x200>;
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+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ blsp1_uart2: serial@78b0000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x0 0x78b0000 0x0 0x200>;
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+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x0 0x078b1000 0x0 0x200>;
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@@ -466,6 +486,36 @@
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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+ };
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+
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+ blsp1_uart4: serial@78b2000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x0 0x078b2000 0x0 0x200>;
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+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ blsp1_uart5: serial@78b3000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x0 0x78b3000 0x0 0x200>;
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+ interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+ };
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+
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+ blsp1_uart6: serial@78b4000 {
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+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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+ reg = <0x0 0x078b4000 0x0 0x200>;
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+ interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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};
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blsp1_spi1: spi@78b5000 {
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