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openwrt/target/linux/realtek/dts/rtl8382_zyxel_gs1900-24ep.dts

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realtek: add support for switch Zyxel GS1900-24EP This device is very similar to the GS1900-24E switch (added in b515ad1), except that the first 12 of 24 ethernet ports are capable of PoE and the physical jacks are in the right order - unlike for the GS1900-24E, where even and uneven ports are flipped (up <-> down on panel). Zyxel version code for this device (-24EP) is: ABTO Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
2024-04-05 15:31:03 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later
#include "rtl8380_zyxel_gs1900.dtsi"
/ {
compatible = "zyxel,gs1900-24ep", "realtek,rtl838x-soc";
treewide: rename ZyXEL to Zyxel The company Zyxel rebranded some years ago. Currently the casing is according to the old branding even for newer devices which already use the new branding. This commit aligns the casing of Zyxel everywhere. Signed-off-by: Goetz Goerisch <ggoerisch@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15652 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2024-06-07 12:42:32 +00:00
model = "Zyxel GS1900-24EP Switch";
realtek: add support for switch Zyxel GS1900-24EP This device is very similar to the GS1900-24E switch (added in b515ad1), except that the first 12 of 24 ethernet ports are capable of PoE and the physical jacks are in the right order - unlike for the GS1900-24E, where even and uneven ports are flipped (up <-> down on panel). Zyxel version code for this device (-24EP) is: ABTO Signed-off-by: Mirko Vogt <mirko-openwrt@nanl.de>
2024-04-05 15:31:03 +00:00
};
&uart1 {
status = "okay";
};
&mdio {
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
};
&switch0 {
ports {
SWITCH_PORT(0, 1, qsgmii)
SWITCH_PORT(1, 2, qsgmii)
SWITCH_PORT(2, 3, qsgmii)
SWITCH_PORT(3, 4, qsgmii)
SWITCH_PORT(4, 5, qsgmii)
SWITCH_PORT(5, 6, qsgmii)
SWITCH_PORT(6, 7, qsgmii)
SWITCH_PORT(7, 8, qsgmii)
SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal)
SWITCH_PORT(10, 11, internal)
SWITCH_PORT(11, 12, internal)
SWITCH_PORT(12, 13, internal)
SWITCH_PORT(13, 14, internal)
SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii)
SWITCH_PORT(17, 18, qsgmii)
SWITCH_PORT(18, 19, qsgmii)
SWITCH_PORT(19, 20, qsgmii)
SWITCH_PORT(20, 21, qsgmii)
SWITCH_PORT(21, 22, qsgmii)
SWITCH_PORT(22, 23, qsgmii)
SWITCH_PORT(23, 24, qsgmii)
};
};