2022-08-31 12:31:02 +00:00
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From e1c55c0ad21daafcb3551b4f5286c1e11c51acc3 Mon Sep 17 00:00:00 2001
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2022-07-12 02:41:30 +00:00
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From: Weijie Gao <weijie.gao@mediatek.com>
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2022-08-31 12:31:02 +00:00
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Date: Wed, 31 Aug 2022 19:04:51 +0800
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Subject: [PATCH 19/32] dt-bindings: pinctrl: mediatek: add a header for common
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2022-07-12 02:41:30 +00:00
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pinconf parameters
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This patch adds a pinctrl header for common pinconf parameters such as
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pull-up/pull-down resistors and drive strengths.
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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include/dt-bindings/pinctrl/mt65xx.h | 41 ++++++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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create mode 100644 include/dt-bindings/pinctrl/mt65xx.h
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--- /dev/null
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+++ b/include/dt-bindings/pinctrl/mt65xx.h
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@@ -0,0 +1,41 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
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+ */
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+
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+#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
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+#define _DT_BINDINGS_PINCTRL_MT65XX_H
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+
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+#define MTK_PIN_NO(x) ((x) << 8)
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+#define MTK_GET_PIN_NO(x) ((x) >> 8)
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+#define MTK_GET_PIN_FUNC(x) ((x) & 0xf)
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+
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+#define MTK_PUPD_SET_R1R0_00 100
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+#define MTK_PUPD_SET_R1R0_01 101
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+#define MTK_PUPD_SET_R1R0_10 102
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+#define MTK_PUPD_SET_R1R0_11 103
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+
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+#define MTK_PULL_SET_RSEL_000 200
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+#define MTK_PULL_SET_RSEL_001 201
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+#define MTK_PULL_SET_RSEL_010 202
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+#define MTK_PULL_SET_RSEL_011 203
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+#define MTK_PULL_SET_RSEL_100 204
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+#define MTK_PULL_SET_RSEL_101 205
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+#define MTK_PULL_SET_RSEL_110 206
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+#define MTK_PULL_SET_RSEL_111 207
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+
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+#define MTK_DRIVE_2mA 2
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+#define MTK_DRIVE_4mA 4
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+#define MTK_DRIVE_6mA 6
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+#define MTK_DRIVE_8mA 8
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+#define MTK_DRIVE_10mA 10
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+#define MTK_DRIVE_12mA 12
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+#define MTK_DRIVE_14mA 14
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+#define MTK_DRIVE_16mA 16
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+#define MTK_DRIVE_20mA 20
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+#define MTK_DRIVE_24mA 24
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+#define MTK_DRIVE_28mA 28
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+#define MTK_DRIVE_32mA 32
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+
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+#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */
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