openwrt/target/linux/mediatek/dts/mt7981b-confiabits-mt7981.dts

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
/dts-v1/;
#include "mt7981.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Confiabits MT7981";
compatible = "confiabits,mt7981", "mediatek,mt7981";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
button-mesh {
label = "mesh";
linux,input-type = <EV_SW>;
linux,code = <BTN_0>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
debounce-interval = <60>;
};
button-reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led-wlan5g {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN;
function-enumerator = <5>;
gpios = <&pio 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
led-wan-red {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WAN;
gpios = <&pio 6 GPIO_ACTIVE_LOW>;
};
led_power: led-power {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
gpios = <&pio 7 GPIO_ACTIVE_LOW>;
};
led-lan1 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
led-lan2 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
led-lan3 {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
gpios = <&pio 11 GPIO_ACTIVE_LOW>;
};
led-wan-blue {
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WAN;
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
};
led-wlan2g {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_WLAN;
function-enumerator = <2>;
gpios = <&pio 34 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
led-mesh {
color = <LED_COLOR_ID_BLUE>;
function = "mesh"; // no LED_FUNCTION_MESH yet
gpios = <&pio 35 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
&watchdog {
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_factory_4 0>;
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
&mdio_bus {
#address-cells = <1>;
#size-cells = <0>;
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
};
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan3";
};
port@4 {
reg = <4>;
label = "wan";
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_factory_4 1>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_flash_pins>;
status = "okay";
spi_nand: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <52000000>;
spi-cal-enable;
spi-cal-mode = "read-data";
spi-cal-datalen = <7>;
spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
spi-cal-addrlen = <5>;
spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
mediatek,nmbm;
mediatek,bmt-max-ratio = <1>;
mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
read-only;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@380000 {
label = "FIP";
reg = <0x380000 0x0200000>;
read-only;
};
partition@580000 {
label = "ubi";
reg = <0x580000 0x4000000>;
compatible = "linux,ubi";
};
};
};
};
&pio {
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
};
};
&usb_phy {
status = "okay";
};
&xhci {
status = "okay";
mediatek,u3p-dis-msk = <0x1>;
};
&wifi {
status = "okay";
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
};