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openwrt/target/linux/qualcommax/Makefile

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ipq807x: add Qualcomm Atheros IPQ807x target Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
2022-02-05 22:40:51 +00:00
include $(TOPDIR)/rules.mk
ARCH:=aarch64
ipq807x: rename target to qualcommax Currently, ipq807x only covers Qualcomm IPQ807x SoC-s. However, Qualcomm also has IPQ60xx and IPQ50xx SoC-s under the AX WiSoC-s and they share a lot of stuff with IPQ807x, especially IPQ60xx so to avoid duplicating kernel patches and everything lets make a common target with per SoC subtargets. Start doing that by renaming ipq807x to qualcommax so that dependencies on ipq807x target can be updated. Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-06-11 17:32:52 +00:00
BOARD:=qualcommax
BOARDNAME:=Qualcomm Atheros 802.11ax WiSoC-s
ipq807x: add QNAP 301w QNAP 301w is a AX WIFI router with 4 1G and 2 10G ports. Specifications: • CPU: Qualcomm IPQ8072A Quad core Cortex-A53 2.2GHz • RAM: 1024MB of DDR3 • Storage: 4GB eMMC (contains kernel and rootfs) / 8MB NOR (contains art and u-boot-env) • Ethernet: 4x 1G RJ45 ports + 2 10G ports (Aquantia AQR113C) • WLAN: 2.4GHz: Qualcomm QCN5024 4x4 (40 MHz) 802.11b/g/n/ax 1174 Mbps PHY rate 5GHz: Qualcomm QCN5054 4x4 (80 MHz) or 2x2 (160 MHz) 802.11a/b/g/n/ac/ax 2402 PHY rate • LEDs: 7 x GPIO-controlled dual color LEDs + 2 GPIO-controlled single color LEDs • Buttons: 1x soft reset / 1x WPS • Power: 12V DC jack A poulated serial header is onboard. RX/TX is working, bootwait is active, secure boot is not enabled. SSH can be activated in the stock firmware, hold WPS button til the second beep (yes the router has a buzzer) SSH is available on port 22200, login with user admin and password "mac address of the router". Installation Instructions: • obtain serial access (https://openwrt.org/inbox/toh/qnap/301w#serial) • stop auto boot • setenv serverip 192.168.10.1 • setenv ipaddr 192.168.10.10 • tftpboot the initramfs image (openwrt-ipq807x-generic-qnap_301w-initramfs-fit-uImage.itb) • bootm • make sure that current_entry is set to "0": "fw_printenv -n current_entry" should be print "0". If not, do "fw_setenv current_entry 0" • copy openwrt-ipq807x-generic-qnap_301w-squashfs-sysupgrade.bin to the device to /tmp folder • sysupgrade -n /tmp/openwrt-ipq807x-generic-qnap_301w-squashfs-sysupgrade.bin this flashes openwrt to the first kernel and rootfs partition (mmcblk0p1 / mmcblk0p4) • reboot Note: this leaves the second kernel / rootfs parition untouched. So if you want to go back to stock, stop u-boot autoboot, "setenv current_entry 1" , "saveenv", "bootipq". Stock firmware should start from the second partition. Then do a firmwareupgrade in the stock gui, that should overwrite the openwrt in the first partitions Make 10G Aquantia phy's work: The aquantia phy's need a firmware to work. This can either be loaded in linux with a userspace tool or in u-boot. I was not successfull to load the firmware in linux (aq-fw-download) but luckily there is aq_load_fw available in u-boot. But first the right firmware needs to write to the 0:ETHPHYFW mtd partition (it is empty on my device) Grab the ethphy firmware image from: https://github.com/kirdesde/nbg7815_gpl/blob/master/target/linux/ipq/ipq807x_64/prebuilt_images/AQR_ethphyfw.mbn and scp that to openwrt. Check the 0:ETHPHYFW partition number: cat /proc/mtd|grep "0:ETHPHYFW", should be mtd10. Backup the 0:ETHPHYFW partition: dd if=/dev/mtd10 of=/tmp/ethphyfw.backup, scp ethphyfw.backup to a save place. Write the new firmware image to the 0:ETHPHYFW partition: "mtd erase /dev/mtd10", "mtd -n write AQR_ethphyfw.mbn /dev/mtd10". Reboot to u-boot. Check if aq_load_fw is working: "aq_load_fw 0", that checks the firmware and if successfull, loads iram and dram to one of the aquantia phy's. If that worked, add the aq_load_fw to the bootcmd: setenv bootcmd "aq_load_fw 0 && aq_load_fw 8 && bootipq" "saveenv" "reset" Board reboots and the firmware load to both phy's should start and then openwrt boots. Check if the 10G ports work. Note: lan port labeled "10G-2" is configured as WAN port as per default. All other port are in the br-lan. This can be changed in the network config. Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de>
2022-01-01 22:20:19 +00:00
FEATURES:=squashfs ramdisk fpu nand rtc emmc
qualcommax: Skip compiling unnecessary dtbs Currently the compile phase of the kernel builds `Image dtbs modules`. However, none of the dtbs that get built are used for the final image. This ends up unnecessarily taking CPU cycles and produces a lot of `WARNINGS` that can lead users to believe there's cause for concern. I believe the same principle can be applied to other targets. ``` DTC arch/arm64/boot/dts/qcom/msm8996-mtp.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) DTC arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dtb arch/arm64/boot/dts/qcom/msm8996.dtsi:2954.36-2962.5: Warning (clocks_property): /soc/clock-controller@6400000: Missing property '#clock-cells' in node /soc/mailbox@9820000 or bad phandle (referred from clocks[2]) ``` Signed-off-by: Sean Khan <datapronix@protonmail.com>
2024-04-08 20:24:12 +00:00
KERNELNAME:=Image
ipq807x: add Qualcomm Atheros IPQ807x target Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
2022-02-05 22:40:51 +00:00
CPU_TYPE:=cortex-a53
qualcommax: add ipq60xx support Introduce support for the Qualcomm IPQ60xx SoC. WiFi support still has to be handled and correctly fix hence this is currently marked as source-only to have a solid base to progress on correct support of this and hope Upstream QUIC publish newers ath11k drivers for this SoC. Co-developed-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Mantas Pucka <mantas@8devices.com> [ improve commit description, add SoB for Robert, make it source-only ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2023-10-14 17:36:38 +00:00
SUBTARGETS:=ipq807x ipq60xx
ipq807x: add Qualcomm Atheros IPQ807x target Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
2022-02-05 22:40:51 +00:00
qualcommax: default to kernel 6.6 6.6 has been in testing on qualcommax for a while so it should be in a good shape, but lets default to it to get a wider audience. Signed-off-by: Robert Marko <robimarko@gmail.com>
2024-03-29 10:38:49 +00:00
KERNEL_PATCHVER:=6.6
ipq807x: add Qualcomm Atheros IPQ807x target Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
2022-02-05 22:40:51 +00:00
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb3 kmod-usb-dwc3 kmod-usb-dwc3-qcom \
kmod-leds-gpio kmod-gpio-button-hotplug \
qualcommax: move ipq807x support to subtarget Now that qualcommax exists as a target and dependencies have been updated let move ipq807x support to subtarget of qualcommax. This is mostly copy/paste with the exception of having to update SSDK and NSS-DP to use CONFIG_TARGET_SUBTARGET. This is a preparation for later addition of IPQ60xx and IPQ50xx support. Signed-off-by: Robert Marko <robimarko@gmail.com>
2023-06-13 20:07:06 +00:00
kmod-qca-nss-dp kmod-ath11k-ahb \
ipq807x: image: fix eMMC flashing/recovery from within initramfs Having initramfs image built with same config as on buildbots: CONFIG_TARGET_MULTI_PROFILE=y CONFIG_TARGET_ALL_PROFILES=y CONFIG_TARGET_PER_DEVICE_ROOTFS=y Its currently impossible to flash/recover the device using that image as losetup is missing: root@OpenWrt:/# sysupgrade -v /tmp/openwrt-ipq807x-generic-prpl_haze-squashfs-sysupgrade.bin ... /lib/upgrade/do_stage2: line 38: losetup: not found Failed to detach all loop devices. Skip this try. So lets fix it by including the needed utils for sysupgrade in DEFAULT_PACKAGES set. Signed-off-by: Petr Štetiar <ynezz@true.cz>
2023-06-05 12:10:44 +00:00
wpad-basic-mbedtls uboot-envtools \
e2fsprogs kmod-fs-ext4 losetup
ipq807x: add Qualcomm Atheros IPQ807x target Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
2022-02-05 22:40:51 +00:00
$(eval $(call BuildTarget))