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openwrt/target/linux/realtek/dts/rtl8393_d-link_dgs-1210-52.dts

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realtek: copy dts/files/patches/configs for 5.15 Copy dts/files/patches/configs from 5.10 to 5.15. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [refresh with updated DGS-1210 dts files] Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-09 13:08:16 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rtl839x.dtsi"
#include "rtl83xx_d-link_dgs-1210_common.dtsi"
#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
realtek: add full SFP support to D-Link DGS-1210-28 series The DGS-1210-28 series was lacking full SFP support due to missing GPIOs. Fortunately, the existing GPIO definitions of DGS-1210-52 match, this adds the required i2c-gpio nodes to the DTS and allows hotplug SFP support. Signed-off-by: Andreas Böhler <dev@aboehler.at> Link: https://github.com/openwrt/openwrt/pull/15616 Signed-off-by: Sander Vanheule <sander@svanheule.net>
2024-06-01 17:14:39 +00:00
#include "rtl83xx_d-link_dgs-1210_gpio_sfp.dtsi"
realtek: copy dts/files/patches/configs for 5.15 Copy dts/files/patches/configs from 5.10 to 5.15. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [refresh with updated DGS-1210 dts files] Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-09 13:08:16 +00:00
/ {
compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
model = "D-Link DGS-1210-52";
};
&ethernet0 {
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
regmap = <&ethernet0>;
#address-cells = <1>;
#size-cells = <0>;
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
/* External phy RTL8214FC */
EXTERNAL_SFP_PHY_FULL(48, 0)
EXTERNAL_SFP_PHY_FULL(49, 1)
EXTERNAL_SFP_PHY_FULL(50, 2)
EXTERNAL_SFP_PHY_FULL(51, 3)
};
};
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii)
SWITCH_PORT(1, 2, qsgmii)
SWITCH_PORT(2, 3, qsgmii)
SWITCH_PORT(3, 4, qsgmii)
SWITCH_PORT(4, 5, qsgmii)
SWITCH_PORT(5, 6, qsgmii)
SWITCH_PORT(6, 7, qsgmii)
SWITCH_PORT(7, 8, qsgmii)
SWITCH_PORT(8, 9, qsgmii)
SWITCH_PORT(9, 10, qsgmii)
SWITCH_PORT(10, 11, qsgmii)
SWITCH_PORT(11, 12, qsgmii)
SWITCH_PORT(12, 13, qsgmii)
SWITCH_PORT(13, 14, qsgmii)
SWITCH_PORT(14, 15, qsgmii)
SWITCH_PORT(15, 16, qsgmii)
SWITCH_PORT(16, 17, qsgmii)
SWITCH_PORT(17, 18, qsgmii)
SWITCH_PORT(18, 19, qsgmii)
SWITCH_PORT(19, 20, qsgmii)
SWITCH_PORT(20, 21, qsgmii)
SWITCH_PORT(21, 22, qsgmii)
SWITCH_PORT(22, 23, qsgmii)
SWITCH_PORT(23, 24, qsgmii)
SWITCH_PORT(24, 25, qsgmii)
SWITCH_PORT(25, 26, qsgmii)
SWITCH_PORT(26, 27, qsgmii)
SWITCH_PORT(27, 28, qsgmii)
SWITCH_PORT(28, 29, qsgmii)
SWITCH_PORT(29, 30, qsgmii)
SWITCH_PORT(30, 31, qsgmii)
SWITCH_PORT(31, 32, qsgmii)
SWITCH_PORT(32, 33, qsgmii)
SWITCH_PORT(33, 34, qsgmii)
SWITCH_PORT(34, 35, qsgmii)
SWITCH_PORT(35, 36, qsgmii)
SWITCH_PORT(36, 37, qsgmii)
SWITCH_PORT(37, 38, qsgmii)
SWITCH_PORT(38, 39, qsgmii)
SWITCH_PORT(39, 40, qsgmii)
SWITCH_PORT(40, 41, qsgmii)
SWITCH_PORT(41, 42, qsgmii)
SWITCH_PORT(42, 43, qsgmii)
SWITCH_PORT(43, 44, qsgmii)
SWITCH_PORT(44, 45, qsgmii)
SWITCH_PORT(45, 46, qsgmii)
SWITCH_PORT(46, 47, qsgmii)
SWITCH_PORT(47, 48, qsgmii)
SWITCH_PORT(48, 49, qsgmii)
SWITCH_PORT(49, 50, qsgmii)
SWITCH_PORT(50, 51, qsgmii)
SWITCH_PORT(51, 52, qsgmii)
/* CPU-Port */
port@52 {
ethernet = <&ethernet0>;
reg = <52>;
phy-mode = "qsgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};