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61b1e75f7d
sh needs runtime-selected atomic backends since there are a number of supported models that use non-forwards-compatible (non-smp-compatible) atomic mechanisms. previously, the code paths for this were highly inefficient since they involved C function calls with multiple branches in the callee and heavy spills in the caller. the new code performs calls the runtime-selected asm fragment from inline asm with extremely minimal clobbers, rather than using a function call. for the sh4a case where the atomic mechanism is known and there is no forward-compatibility issue, the movli.l and movco.l instructions are provided as a_ll and a_sc, allowing the new shared atomic.h to generate efficient inline versions of all the basic atomic operations without needing a cas loop.
47 lines
961 B
C
47 lines
961 B
C
#if defined(__SH4A__)
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#define a_ll a_ll
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static inline int a_ll(volatile int *p)
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{
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int v;
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__asm__ __volatile__ ("movli.l @%1, %0" : "=z"(v) : "r"(p), "m"(*p));
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return v;
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}
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#define a_sc a_sc
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static inline int a_sc(volatile int *p, int v)
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{
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int r;
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__asm__ __volatile__ (
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"movco.l %2, @%3 ; movt %0"
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: "=r"(r), "=m"(*p) : "z"(v), "r"(p) : "memory", "cc");
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return r;
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}
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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__asm__ __volatile__ ("synco" : : "memory");
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}
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#define a_pre_llsc a_barrier
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#define a_post_llsc a_barrier
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#else
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#define a_cas a_cas
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__attribute__((__visibility__("hidden"))) extern const void *__sh_cas_ptr;
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static inline int a_cas(volatile int *p, int t, int s)
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{
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register int r1 __asm__("r1");
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register int r2 __asm__("r2") = t;
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register int r3 __asm__("r3") = s;
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__asm__ __volatile__ (
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"jsr @%4 ; nop"
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: "=r"(r1), "+r"(r3) : "z"(p), "r"(r2), "r"(__sh_cas_ptr)
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: "memory", "pr", "cc");
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return r3;
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}
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#endif
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