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6d99ad91e8
mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used.
19 lines
435 B
C
19 lines
435 B
C
static inline struct pthread *__pthread_self()
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{
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#if __mips_isa_rev < 2
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register char *tp __asm__("$3");
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__asm__ __volatile__ (".word 0x7c03e83b" : "=r" (tp) );
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#else
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char *tp;
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__asm__ __volatile__ ("rdhwr %0, $29" : "=r" (tp) );
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#endif
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return (pthread_t)(tp - 0x7000 - sizeof(struct pthread));
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}
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#define TLS_ABOVE_TP
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#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread) + 0x7000)
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#define DTP_OFFSET 0x8000
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#define MC_PC pc
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