mirror of
git://git.musl-libc.org/musl
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90e51e45f5
the a_cas_l, a_swap_l, a_swap_p, and a_store_l operations were probably used a long time ago when only i386 and x86_64 were supported. as other archs were added, support for them was inconsistent, and they are obviously not in use at present. having them around potentially confuses readers working on new ports, and the type-punning hacks and inconsistent use of types in their definitions is not a style I wish to perpetuate in the source tree, so removing them seems appropriate.
147 lines
2.6 KiB
C
147 lines
2.6 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_l(unsigned long x)
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{
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static const char debruijn32[32] = {
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0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13,
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31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14
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};
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return debruijn32[(x&-x)*0x076be629 >> 27];
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}
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static inline int a_ctz_64(uint64_t x)
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{
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uint32_t y = x;
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if (!y) {
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y = x>>32;
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return 32 + a_ctz_l(y);
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}
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return a_ctz_l(y);
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}
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#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define MEM_BARRIER "dmb ish"
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#else
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#define MEM_BARRIER "mcr p15,0,r0,c7,c10,5"
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#endif
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static inline int __k_cas(int t, int s, volatile int *p)
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{
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int ret;
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__asm__(
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" " MEM_BARRIER "\n"
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"1: ldrex %0,%3\n"
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" subs %0,%0,%1\n"
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#ifdef __thumb__
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" itt eq\n"
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#endif
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" strexeq %0,%2,%3\n"
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" teqeq %0,#1\n"
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" beq 1b\n"
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" " MEM_BARRIER "\n"
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: "=&r"(ret)
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: "r"(t), "r"(s), "Q"(*p)
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: "memory", "cc" );
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return ret;
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}
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#else
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#define __k_cas ((int (*)(int, int, volatile int *))0xffff0fc0)
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#endif
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static inline int a_cas(volatile int *p, int t, int s)
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{
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int old;
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for (;;) {
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if (!__k_cas(t, s, p))
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return t;
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if ((old=*p) != t)
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return old;
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}
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}
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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return (void *)a_cas(p, (int)t, (int)s);
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}
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static inline int a_swap(volatile int *x, int v)
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{
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int old;
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do old = *x;
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while (__k_cas(old, v, x));
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return old;
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}
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static inline int a_fetch_add(volatile int *x, int v)
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{
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int old;
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do old = *x;
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while (__k_cas(old, old+v, x));
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return old;
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}
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static inline void a_inc(volatile int *x)
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{
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a_fetch_add(x, 1);
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}
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static inline void a_dec(volatile int *x)
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{
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a_fetch_add(x, -1);
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}
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static inline void a_store(volatile int *p, int x)
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{
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while (__k_cas(*p, x, p));
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}
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static inline void a_spin()
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{
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}
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static inline void a_crash()
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{
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*(volatile char *)0=0;
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}
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static inline void a_and(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (__k_cas(old, old&v, p));
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}
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static inline void a_or(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (__k_cas(old, old|v, p));
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}
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static inline void a_or_l(volatile void *p, long v)
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{
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a_or(p, v);
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_and((int *)p, u.r[0]);
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a_and((int *)p+1, u.r[1]);
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_or((int *)p, u.r[0]);
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a_or((int *)p+1, u.r[1]);
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}
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#endif
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