mirror of
git://git.musl-libc.org/musl
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5a9c8c05a5
commit 3c43c0761e fixed missing
synchronization in the atomic store operation for i386 and x86_64, but
opted to use mfence for the barrier on x86_64 where it's always
available. however, in practice mfence is significantly slower than
the barrier approach used on i386 (a nop-like lock orl operation).
this commit changes x86_64 (and x32) to use the faster barrier.
106 lines
2.1 KiB
C
106 lines
2.1 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_64(uint64_t x)
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{
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__asm__( "bsf %1,%0" : "=r"(x) : "r"(x) );
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return x;
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}
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static inline int a_ctz_l(unsigned long x)
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{
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__asm__( "bsf %1,%0" : "=r"(x) : "r"(x) );
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return x;
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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__asm__( "lock ; and %1, %0"
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: "=m"(*p) : "r"(v) : "memory" );
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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__asm__( "lock ; or %1, %0"
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: "=m"(*p) : "r"(v) : "memory" );
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}
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static inline void a_or_l(volatile void *p, long v)
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{
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__asm__( "lock ; or %1, %0"
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: "=m"(*(long *)p) : "r"(v) : "memory" );
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}
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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__asm__( "lock ; cmpxchg %3, %1"
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: "=a"(t), "=m"(*(long *)p) : "a"(t), "r"(s) : "memory" );
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return t;
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}
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static inline int a_cas(volatile int *p, int t, int s)
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{
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__asm__( "lock ; cmpxchg %3, %1"
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: "=a"(t), "=m"(*p) : "a"(t), "r"(s) : "memory" );
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return t;
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}
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static inline void a_or(volatile int *p, int v)
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{
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__asm__( "lock ; or %1, %0"
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: "=m"(*p) : "r"(v) : "memory" );
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}
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static inline void a_and(volatile int *p, int v)
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{
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__asm__( "lock ; and %1, %0"
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: "=m"(*p) : "r"(v) : "memory" );
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}
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static inline int a_swap(volatile int *x, int v)
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{
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__asm__( "xchg %0, %1" : "=r"(v), "=m"(*x) : "0"(v) : "memory" );
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return v;
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}
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static inline int a_fetch_add(volatile int *x, int v)
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{
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__asm__( "lock ; xadd %0, %1" : "=r"(v), "=m"(*x) : "0"(v) : "memory" );
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return v;
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}
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static inline void a_inc(volatile int *x)
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{
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__asm__( "lock ; incl %0" : "=m"(*x) : "m"(*x) : "memory" );
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}
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static inline void a_dec(volatile int *x)
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{
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__asm__( "lock ; decl %0" : "=m"(*x) : "m"(*x) : "memory" );
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}
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static inline void a_store(volatile int *p, int x)
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{
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__asm__( "mov %1, %0 ; lock ; orl $0,(%%rsp)" : "=m"(*p) : "r"(x) : "memory" );
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}
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static inline void a_spin()
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{
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__asm__ __volatile__( "pause" : : : "memory" );
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}
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static inline void a_barrier()
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{
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__asm__ __volatile__( "" : : : "memory" );
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}
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static inline void a_crash()
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{
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__asm__ __volatile__( "hlt" : : : "memory" );
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}
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#endif
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