mirror of
git://git.musl-libc.org/musl
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036eaa24cf
linux guarantees ll/sc are always available. on mips1, they will be emulated by the kernel. thus they are part of the linux mips1 abi and safe to use.
200 lines
3.6 KiB
C
200 lines
3.6 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_l(unsigned long x)
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{
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static const char debruijn32[32] = {
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0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13,
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31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14
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};
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return debruijn32[(x&-x)*0x076be629 >> 27];
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}
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static inline int a_ctz_64(uint64_t x)
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{
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uint32_t y = x;
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if (!y) {
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y = x>>32;
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return 32 + a_ctz_l(y);
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}
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return a_ctz_l(y);
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}
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static inline int a_cas(volatile int *p, int t, int s)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%2)\n"
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" bne %0, %3, 1f\n"
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" addu %1, %4, $0\n"
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" sc %1, 0(%2)\n"
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" beq %1, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(t), "=&r"(dummy) : "r"(p), "r"(t), "r"(s) : "memory" );
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return t;
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}
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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return (void *)a_cas(p, (int)t, (int)s);
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}
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static inline long a_cas_l(volatile void *p, long t, long s)
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{
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return a_cas(p, t, s);
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}
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static inline int a_swap(volatile int *x, int v)
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{
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int old, dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%2)\n"
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" addu %1, %3, $0\n"
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" sc %1, 0(%2)\n"
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" beq %1, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(old), "=&r"(dummy) : "r"(x), "r"(v) : "memory" );
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return old;
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}
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static inline int a_fetch_add(volatile int *x, int v)
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{
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int old, dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%2)\n"
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" addu %1, %0, %3\n"
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" sc %1, 0(%2)\n"
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" beq %1, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(old), "=&r"(dummy) : "r"(x), "r"(v) : "memory" );
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return old;
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}
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static inline void a_inc(volatile int *x)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%1)\n"
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" addu %0, %0, 1\n"
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" sc %0, 0(%1)\n"
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" beq %0, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(dummy) : "r"(x) : "memory" );
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}
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static inline void a_dec(volatile int *x)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%1)\n"
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" subu %0, %0, 1\n"
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" sc %0, 0(%1)\n"
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" beq %0, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(dummy) : "r"(x) : "memory" );
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}
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static inline void a_store(volatile int *p, int x)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%1)\n"
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" addu %0, %2, $0\n"
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" sc %0, 0(%1)\n"
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" beq %0, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(dummy) : "r"(p), "r"(x) : "memory" );
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}
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static inline void a_spin()
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{
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}
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static inline void a_crash()
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{
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*(volatile char *)0=0;
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}
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static inline void a_and(volatile int *p, int v)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%1)\n"
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" and %0, %0, %2\n"
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" sc %0, 0(%1)\n"
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" beq %0, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(dummy) : "r"(p), "r"(v) : "memory" );
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}
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static inline void a_or(volatile int *p, int v)
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{
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int dummy;
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__asm__ __volatile__(
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".set push\n"
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".set mips2\n"
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".set noreorder\n"
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"1: ll %0, 0(%1)\n"
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" or %0, %0, %2\n"
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" sc %0, 0(%1)\n"
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" beq %0, $0, 1b\n"
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" nop\n"
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"1: \n"
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".set pop\n"
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: "=&r"(dummy) : "r"(p), "r"(v) : "memory" );
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_and((int *)p, u.r[0]);
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a_and((int *)p+1, u.r[1]);
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_or((int *)p, u.r[0]);
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a_or((int *)p+1, u.r[1]);
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}
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#endif
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