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6d99ad91e8
mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used.
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
#ifndef __RELOC_H__
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#define __RELOC_H__
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#define _GNU_SOURCE
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#include <endian.h>
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#if __mips_isa_rev >= 6
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#define ISA_SUFFIX "r6"
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#else
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#define ISA_SUFFIX ""
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#endif
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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#define ENDIAN_SUFFIX "el"
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#else
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#define ENDIAN_SUFFIX ""
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#endif
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#ifdef __mips_soft_float
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#define FP_SUFFIX "-sf"
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#else
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#define FP_SUFFIX ""
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#endif
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#define LDSO_ARCH "mips64" ISA_SUFFIX ENDIAN_SUFFIX FP_SUFFIX
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#define TPOFF_K (-0x7000)
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#define REL_SYM_OR_REL 4611
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#define REL_PLT R_MIPS_JUMP_SLOT
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#define REL_COPY R_MIPS_COPY
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#define REL_DTPMOD R_MIPS_TLS_DTPMOD64
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#define REL_DTPOFF R_MIPS_TLS_DTPREL64
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#define REL_TPOFF R_MIPS_TLS_TPREL64
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#undef R_TYPE
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#undef R_SYM
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#undef R_INFO
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#define R_TYPE(x) (be64toh(x)&0x7fffffff)
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#define R_SYM(x) (be32toh(be64toh(x)>>32))
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#define R_INFO(s,t) (htobe64((uint64_t)htobe32(s)<<32 | (uint64_t)t))
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#define NEED_MIPS_GOT_RELOCS 1
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#define DT_DEBUG_INDIRECT DT_MIPS_RLD_MAP
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#define ARCH_SYM_REJECT_UND(s) (!((s)->st_other & STO_MIPS_PLT))
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#define CRTJMP(pc,sp) __asm__ __volatile__( \
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"move $sp,%1 ; jr %0" : : "r"(pc), "r"(sp) : "memory" )
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#define GETFUNCSYM(fp, sym, got) __asm__ ( \
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".hidden " #sym "\n" \
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".set push \n" \
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".set noreorder \n" \
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".align 8 \n" \
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" bal 1f \n" \
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" nop \n" \
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" .gpdword . \n" \
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" .gpdword " #sym " \n" \
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"1: ld %0, ($ra) \n" \
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" dsubu %0, $ra, %0 \n" \
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" ld $ra, 8($ra) \n" \
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" daddu %0, %0, $ra \n" \
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".set pop \n" \
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: "=r"(*(fp)) : : "memory", "ra" )
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#endif
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