musl/arch
Rich Felker 92637bb0d8 prevent reordering of or1k and powerpc thread pointer loads
other archs use asm for the thread pointer load, so making that asm
volatile is sufficient to inform the compiler that it has a "side
effect" (crashing or giving the wrong result if the thread pointer was
not yet initialized) that prevents reordering. however, powerpc and
or1k have dedicated general purpose registers for the thread pointer
and did not need to use any asm to access it; instead, "local register
variables with a specified register" were used. however, there is no
specification for ordering constraints on this type of usage, and
presumably use of the thread pointer could be reordered across its
initialization.

to impose an ordering, I have added empty volatile asm blocks that
produce the "local register variable with a specified register" as
an output constraint.
2015-10-15 12:08:51 -04:00
..
aarch64 fix namespace violations in aarch64/bits/termios.h 2015-09-15 14:28:07 -04:00
arm mark arm thread-pointer-loading inline asm as volatile 2015-10-15 12:04:48 -04:00
i386 introduce new symbol-lookup-free rcrt1/dlstart stage chaining 2015-09-17 06:30:55 +00:00
microblaze new dlstart stage-2 chaining for microblaze 2015-09-17 07:20:36 +00:00
mips add comment documenting hard-coded opcode for reading mips thread pointer 2015-10-15 00:55:41 -04:00
or1k prevent reordering of or1k and powerpc thread pointer loads 2015-10-15 12:08:51 -04:00
powerpc prevent reordering of or1k and powerpc thread pointer loads 2015-10-15 12:08:51 -04:00
sh fix signal return for sh/fdpic 2015-09-23 18:33:49 +00:00
x32 new dlstart stage-2 chaining for x86_64 and x32 2015-09-17 07:28:44 +00:00
x86_64 new dlstart stage-2 chaining for x86_64 and x32 2015-09-17 07:28:44 +00:00