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6d99ad91e8
mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used.
57 lines
966 B
C
57 lines
966 B
C
#if __mips_isa_rev < 6
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#define LLSC_M "m"
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#else
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#define LLSC_M "ZC"
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#endif
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#define a_ll a_ll
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static inline int a_ll(volatile int *p)
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{
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int v;
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__asm__ __volatile__ (
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"ll %0, %1"
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: "=r"(v) : LLSC_M(*p));
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return v;
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}
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#define a_sc a_sc
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static inline int a_sc(volatile int *p, int v)
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{
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int r;
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__asm__ __volatile__ (
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"sc %0, %1"
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: "=r"(r), "="LLSC_M(*p) : "0"(v) : "memory");
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return r;
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}
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#define a_ll_p a_ll_p
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static inline void *a_ll_p(volatile void *p)
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{
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void *v;
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__asm__ __volatile__ (
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"lld %0, %1"
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: "=r"(v) : LLSC_M(*(void *volatile *)p));
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return v;
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}
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#define a_sc_p a_sc_p
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static inline int a_sc_p(volatile void *p, void *v)
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{
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long r;
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__asm__ __volatile__ (
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"scd %0, %1"
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: "=r"(r), "="LLSC_M(*(void *volatile *)p) : "0"(v) : "memory");
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return r;
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}
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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#define a_pre_llsc a_barrier
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#define a_post_llsc a_barrier
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#undef LLSC_M
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