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610c5a8524
In TLS variant I the TLS is above TP (or above a fixed offset from TP) but on some targets there is a reserved gap above TP before TLS starts. This matters for the local-exec tls access model when the offsets of TLS variables from the TP are hard coded by the linker into the executable, so the libc must compute these offsets the same way as the linker. The tls offset of the main module has to be alignup(GAP_ABOVE_TP, main_tls_align). If there is no TLS in the main module then the gap can be ignored since musl does not use it and the tls access models of shared libraries are not affected. The previous setup only worked if (tls_align & -GAP_ABOVE_TP) == 0 (i.e. TLS did not require large alignment) because the gap was treated as a fixed offset from TP. Now the TP points at the end of the pthread struct (which is aligned) and there is a gap above it (which may also need alignment). The fix required changing TP_ADJ and __pthread_self on affected targets (aarch64, arm and sh) and in the tlsdesc asm the offset to access the dtv changed too.
34 lines
840 B
C
34 lines
840 B
C
#if ((__ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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static inline pthread_t __pthread_self()
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{
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char *p;
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__asm__ __volatile__ ( "mrc p15,0,%0,c13,c0,3" : "=r"(p) );
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return (void *)(p-sizeof(struct pthread));
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}
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#else
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#if __ARM_ARCH_4__ || __ARM_ARCH_4T__ || __ARM_ARCH == 4
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#define BLX "mov lr,pc\n\tbx"
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#else
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#define BLX "blx"
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#endif
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static inline pthread_t __pthread_self()
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{
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extern uintptr_t __attribute__((__visibility__("hidden"))) __a_gettp_ptr;
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register uintptr_t p __asm__("r0");
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__asm__ __volatile__ ( BLX " %1" : "=r"(p) : "r"(__a_gettp_ptr) : "cc", "lr" );
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return (void *)(p-sizeof(struct pthread));
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}
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#endif
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#define TLS_ABOVE_TP
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#define GAP_ABOVE_TP 8
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#define TP_ADJ(p) ((char *)(p) + sizeof(struct pthread))
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#define MC_PC arm_pc
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