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390f93ef69
If we're building for sh4a, the compiler is already free to use instructions only available on sh4a, so we can do the same and inline the llsc atomics. If we're building for an older processor, we still do the same runtime atomics selection as before.
169 lines
3.5 KiB
C
169 lines
3.5 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_l(unsigned long x)
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{
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static const char debruijn32[32] = {
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0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13,
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31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14
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};
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return debruijn32[(x&-x)*0x076be629 >> 27];
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}
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static inline int a_ctz_64(uint64_t x)
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{
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uint32_t y = x;
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if (!y) {
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y = x>>32;
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return 32 + a_ctz_l(y);
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}
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return a_ctz_l(y);
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}
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#define LLSC_CLOBBERS "r0", "t", "memory"
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#define LLSC_START(mem) "synco\n" \
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"0: movli.l @" mem ", r0\n"
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#define LLSC_END(mem) \
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"1: movco.l r0, @" mem "\n" \
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" bf 0b\n" \
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" synco\n"
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static inline int __sh_cas_llsc(volatile int *p, int t, int s)
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{
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int old;
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__asm__ __volatile__(
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LLSC_START("%1")
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" mov r0, %0\n"
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" cmp/eq %0, %2\n"
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" bf 1f\n"
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" mov %3, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(p), "r"(t), "r"(s) : LLSC_CLOBBERS);
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return old;
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}
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static inline int __sh_swap_llsc(volatile int *x, int v)
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{
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int old;
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__asm__ __volatile__(
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LLSC_START("%1")
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" mov r0, %0\n"
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" mov %2, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(x), "r"(v) : LLSC_CLOBBERS);
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return old;
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}
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static inline int __sh_fetch_add_llsc(volatile int *x, int v)
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{
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int old;
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__asm__ __volatile__(
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LLSC_START("%1")
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" mov r0, %0\n"
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" add %2, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(x), "r"(v) : LLSC_CLOBBERS);
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return old;
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}
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static inline void __sh_store_llsc(volatile int *p, int x)
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{
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__asm__ __volatile__(
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" synco\n"
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" mov.l %1, @%0\n"
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" synco\n"
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: : "r"(p), "r"(x) : "memory");
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}
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static inline void __sh_and_llsc(volatile int *x, int v)
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{
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__asm__ __volatile__(
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LLSC_START("%0")
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" and %1, r0\n"
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LLSC_END("%0")
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: : "r"(x), "r"(v) : LLSC_CLOBBERS);
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}
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static inline void __sh_or_llsc(volatile int *x, int v)
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{
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__asm__ __volatile__(
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LLSC_START("%0")
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" or %1, r0\n"
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LLSC_END("%0")
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: : "r"(x), "r"(v) : LLSC_CLOBBERS);
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}
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#ifdef __SH4A__
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#define a_cas(p,t,s) __sh_cas_llsc(p,t,s)
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#define a_swap(x,v) __sh_swap_llsc(x,v)
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#define a_fetch_add(x,v) __sh_fetch_add_llsc(x, v)
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#define a_store(x,v) __sh_store_llsc(x, v)
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#define a_and(x,v) __sh_and_llsc(x, v)
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#define a_or(x,v) __sh_or_llsc(x, v)
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#else
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int __sh_cas(volatile int *, int, int);
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int __sh_swap(volatile int *, int);
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int __sh_fetch_add(volatile int *, int);
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void __sh_store(volatile int *, int);
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void __sh_and(volatile int *, int);
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void __sh_or(volatile int *, int);
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#define a_cas(p,t,s) __sh_cas(p,t,s)
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#define a_swap(x,v) __sh_swap(x,v)
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#define a_fetch_add(x,v) __sh_fetch_add(x, v)
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#define a_store(x,v) __sh_store(x, v)
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#define a_and(x,v) __sh_and(x, v)
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#define a_or(x,v) __sh_or(x, v)
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#endif
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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return (void *)a_cas(p, (int)t, (int)s);
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}
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static inline void a_inc(volatile int *x)
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{
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a_fetch_add(x, 1);
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}
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static inline void a_dec(volatile int *x)
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{
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a_fetch_add(x, -1);
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}
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#define a_spin a_barrier
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static inline void a_barrier()
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{
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a_cas(&(int){0}, 0, 0);
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}
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static inline void a_crash()
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{
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*(volatile char *)0=0;
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}
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static inline void a_or_l(volatile void *p, long v)
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{
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a_or(p, v);
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_and((int *)p, u.r[0]);
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a_and((int *)p+1, u.r[1]);
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_or((int *)p, u.r[0]);
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a_or((int *)p+1, u.r[1]);
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}
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#endif
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