mirror of
git://git.musl-libc.org/musl
synced 2024-12-17 12:14:42 +00:00
8c0a3d9e5c
based on initial work by rdp, with heavy modifications. some features including threads are untested because qemu app-level emulation seems to be broken and I do not have a proper system image for testing.
152 lines
2.8 KiB
C
152 lines
2.8 KiB
C
#ifndef _INTERNAL_ATOMIC_H
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#define _INTERNAL_ATOMIC_H
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#include <stdint.h>
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static inline int a_ctz_l(unsigned long x)
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{
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static const char debruijn32[32] = {
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0, 1, 23, 2, 29, 24, 19, 3, 30, 27, 25, 11, 20, 8, 4, 13,
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31, 22, 28, 18, 26, 10, 7, 12, 21, 17, 9, 6, 16, 5, 15, 14
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};
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return debruijn32[(x&-x)*0x076be629 >> 27];
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}
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static inline int a_ctz_64(uint64_t x)
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{
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uint32_t y = x;
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if (!y) {
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y = x>>32;
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return 32 + a_ctz_l(y);
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}
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return a_ctz_l(y);
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}
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static inline int a_cas_1(volatile int *p, int t, int s)
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{
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register int tmp;
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do {
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__asm__ __volatile__ ("lwx %0, %1, r0"
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: "=r"(tmp) : "r"(p) : "memory");
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if (tmp != t) return tmp;
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__asm__ __volatile__ ("swx %2, %1, r0 ; addic %0, r0, 0"
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: "=r"(tmp) : "r"(p), "r"(s) : "cc", "memory");
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} while (tmp);
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return t;
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}
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static inline int a_cas(volatile int *p, int t, int s)
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{
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register int old, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" rsubk %1, %0, %3\n"
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" bnei %1, 1f\n"
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" swx %4, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(old), "=&r"(tmp)
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: "r"(p), "r"(t), "r"(s)
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: "cc", "memory" );
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return old;
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}
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static inline void *a_cas_p(volatile void *p, void *t, void *s)
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{
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return (void *)a_cas(p, (int)t, (int)s);
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}
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static inline long a_cas_l(volatile void *p, long t, long s)
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{
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return a_cas(p, t, s);
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}
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static inline int a_swap(volatile int *x, int v)
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{
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register int old, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" swx %3, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(old), "=&r"(tmp)
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: "r"(x), "r"(v)
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: "cc", "memory" );
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return old;
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}
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static inline int a_fetch_add(volatile int *x, int v)
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{
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register int new, tmp;
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__asm__ __volatile__ (
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" addi %0, r0, 0\n"
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"1: lwx %0, %2, r0\n"
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" addk %0, %0, %3\n"
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" swx %0, %2, r0\n"
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" addic %1, r0, 0\n"
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" bnei %1, 1b\n"
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"1: "
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: "=&r"(new), "=&r"(tmp)
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: "r"(x), "r"(v)
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: "cc", "memory" );
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return new-v;
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}
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static inline void a_inc(volatile int *x)
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{
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a_fetch_add(x, 1);
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}
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static inline void a_dec(volatile int *x)
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{
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a_fetch_add(x, -1);
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}
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static inline void a_store(volatile int *p, int x)
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{
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*p=x;
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}
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static inline void a_spin()
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{
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}
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static inline void a_crash()
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{
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*(volatile char *)0=0;
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}
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static inline void a_and(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (a_cas(p, old, old&v) != old);
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}
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static inline void a_or(volatile int *p, int v)
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{
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int old;
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do old = *p;
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while (a_cas(p, old, old|v) != old);
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}
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static inline void a_and_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_and((int *)p, u.r[0]);
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a_and((int *)p+1, u.r[1]);
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}
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static inline void a_or_64(volatile uint64_t *p, uint64_t v)
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{
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union { uint64_t v; uint32_t r[2]; } u = { v };
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a_or((int *)p, u.r[0]);
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a_or((int *)p+1, u.r[1]);
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}
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#endif
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