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7be59733d7
When the soft-float ABI for PowerPC was added in commit
5a92dd95c7, with Freescale cpus using
the alternative SPE FPU as the main use case, it was noted that we
could probably support hard float on them, but that it would involve
determining some difficult ABI constraints. This commit is the
completion of that work.
The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed
ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility
are problematic for the same reason they're problematic on ARM, where
optional float-related parts of the register file are "call-saved if
present". This requires testing __hwcap, which is now done.
In keeping with the existing powerpc-sf subarch definition, which did
not have fenv, the fenv macros are not defined for SPE and the SPEFSCR
control register is left (and assumed to start in) the default mode.
32 lines
855 B
C
32 lines
855 B
C
#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
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#define FP_SUFFIX "-sf"
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#else
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#define FP_SUFFIX ""
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#endif
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#define LDSO_ARCH "powerpc" FP_SUFFIX
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#define TPOFF_K (-0x7000)
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#define REL_SYMBOLIC R_PPC_ADDR32
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#define REL_USYMBOLIC R_PPC_UADDR32
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#define REL_GOT R_PPC_GLOB_DAT
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#define REL_PLT R_PPC_JMP_SLOT
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#define REL_RELATIVE R_PPC_RELATIVE
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#define REL_COPY R_PPC_COPY
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#define REL_DTPMOD R_PPC_DTPMOD32
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#define REL_DTPOFF R_PPC_DTPREL32
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#define REL_TPOFF R_PPC_TPREL32
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#define CRTJMP(pc,sp) __asm__ __volatile__( \
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"mr 1,%1 ; mtlr %0 ; blr" : : "r"(pc), "r"(sp) : "memory" )
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#define GETFUNCSYM(fp, sym, got) __asm__ ( \
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".hidden " #sym " \n" \
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" bl 1f \n" \
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" .long " #sym "-. \n" \
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"1: mflr %1 \n" \
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" lwz %0, 0(%1) \n" \
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" add %0, %0, %1 \n" \
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: "=r"(*(fp)), "=r"((int){0}) : : "memory", "lr" )
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