mirror of git://git.musl-libc.org/musl
overhaul sh atomics for new atomics framework, add j-core cas.l backend
sh needs runtime-selected atomic backends since there are a number of supported models that use non-forwards-compatible (non-smp-compatible) atomic mechanisms. previously, the code paths for this were highly inefficient since they involved C function calls with multiple branches in the callee and heavy spills in the caller. the new code performs calls the runtime-selected asm fragment from inline asm with extremely minimal clobbers, rather than using a function call. for the sh4a case where the atomic mechanism is known and there is no forward-compatibility issue, the movli.l and movco.l instructions are provided as a_ll and a_sc, allowing the new shared atomic.h to generate efficient inline versions of all the basic atomic operations without needing a cas loop.
This commit is contained in:
Rich Felker
parent
1315596b51
commit
61b1e75f7d
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@ -1,96 +1,46 @@
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#define LLSC_CLOBBERS "r0", "t", "memory"
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#define LLSC_START(mem) "synco\n" \
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"0: movli.l @" mem ", r0\n"
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#define LLSC_END(mem) \
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"1: movco.l r0, @" mem "\n" \
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" bf 0b\n" \
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" synco\n"
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#if defined(__SH4A__)
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static inline int __sh_cas_llsc(volatile int *p, int t, int s)
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#define a_ll a_ll
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static inline int a_ll(volatile int *p)
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{
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int old;
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__asm__ __volatile__(
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LLSC_START("%1")
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" mov r0, %0\n"
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" cmp/eq %0, %2\n"
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" bf 1f\n"
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" mov %3, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(p), "r"(t), "r"(s) : LLSC_CLOBBERS);
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return old;
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int v;
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__asm__ __volatile__ ("movli.l @%1, %0" : "=z"(v) : "r"(p), "m"(*p));
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return v;
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}
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static inline int __sh_swap_llsc(volatile int *x, int v)
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#define a_sc a_sc
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static inline int a_sc(volatile int *p, int v)
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{
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int old;
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int r;
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__asm__ __volatile__ (
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LLSC_START("%1")
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" mov r0, %0\n"
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" mov %2, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(x), "r"(v) : LLSC_CLOBBERS);
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return old;
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"movco.l %2, @%3 ; movt %0"
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: "=r"(r), "=m"(*p) : "z"(v), "r"(p) : "memory", "cc");
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return r;
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}
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static inline int __sh_fetch_add_llsc(volatile int *x, int v)
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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int old;
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__asm__ __volatile__(
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LLSC_START("%1")
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" mov r0, %0\n"
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" add %2, r0\n"
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LLSC_END("%1")
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: "=&r"(old) : "r"(x), "r"(v) : LLSC_CLOBBERS);
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return old;
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__asm__ __volatile__ ("synco" : : "memory");
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}
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static inline void __sh_store_llsc(volatile int *p, int x)
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{
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__asm__ __volatile__(
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" synco\n"
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" mov.l %1, @%0\n"
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" synco\n"
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: : "r"(p), "r"(x) : "memory");
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}
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#define a_pre_llsc a_barrier
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#define a_post_llsc a_barrier
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static inline void __sh_and_llsc(volatile int *x, int v)
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{
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__asm__ __volatile__(
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LLSC_START("%0")
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" and %1, r0\n"
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LLSC_END("%0")
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: : "r"(x), "r"(v) : LLSC_CLOBBERS);
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}
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static inline void __sh_or_llsc(volatile int *x, int v)
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{
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__asm__ __volatile__(
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LLSC_START("%0")
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" or %1, r0\n"
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LLSC_END("%0")
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: : "r"(x), "r"(v) : LLSC_CLOBBERS);
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}
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#ifdef __SH4A__
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#define a_cas(p,t,s) __sh_cas_llsc(p,t,s)
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#define a_swap(x,v) __sh_swap_llsc(x,v)
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#define a_fetch_add(x,v) __sh_fetch_add_llsc(x, v)
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#define a_store(x,v) __sh_store_llsc(x, v)
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#define a_and(x,v) __sh_and_llsc(x, v)
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#define a_or(x,v) __sh_or_llsc(x, v)
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#else
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int __sh_cas(volatile int *, int, int);
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int __sh_swap(volatile int *, int);
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int __sh_fetch_add(volatile int *, int);
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void __sh_store(volatile int *, int);
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void __sh_and(volatile int *, int);
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void __sh_or(volatile int *, int);
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#define a_cas a_cas
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__attribute__((__visibility__("hidden"))) extern const void *__sh_cas_ptr;
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static inline int a_cas(volatile int *p, int t, int s)
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{
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register int r1 __asm__("r1");
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register int r2 __asm__("r2") = t;
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register int r3 __asm__("r3") = s;
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__asm__ __volatile__ (
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"jsr @%4 ; nop"
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: "=r"(r1), "+r"(r3) : "z"(p), "r"(r2), "r"(__sh_cas_ptr)
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: "memory", "pr", "cc");
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return r3;
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}
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#define a_cas(p,t,s) __sh_cas(p,t,s)
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#define a_swap(x,v) __sh_swap(x,v)
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#define a_fetch_add(x,v) __sh_fetch_add(x, v)
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#define a_store(x,v) __sh_store(x, v)
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#define a_and(x,v) __sh_and(x, v)
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#define a_or(x,v) __sh_or(x, v)
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#endif
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@ -1,158 +0,0 @@
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#ifndef __SH4A__
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#include "sh_atomic.h"
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#include "atomic.h"
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#include "libc.h"
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static inline unsigned mask()
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{
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unsigned sr;
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__asm__ __volatile__ ( "\n"
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" stc sr,r0 \n"
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" mov r0,%0 \n"
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" or #0xf0,r0 \n"
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" ldc r0,sr \n"
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: "=&r"(sr) : : "memory", "r0" );
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return sr;
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}
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static inline void unmask(unsigned sr)
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{
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__asm__ __volatile__ ( "ldc %0,sr" : : "r"(sr) : "memory" );
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}
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/* gusa is a hack in the kernel which lets you create a sequence of instructions
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* which will be restarted if the process is preempted in the middle of the
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* sequence. It will do for implementing atomics on non-smp systems. ABI is:
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* r0 = address of first instruction after the atomic sequence
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* r1 = original stack pointer
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* r15 = -1 * length of atomic sequence in bytes
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*/
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#define GUSA_CLOBBERS "r0", "r1", "memory"
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#define GUSA_START(mem,old,nop) \
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" .align 2\n" \
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" mova 1f, r0\n" \
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nop \
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" mov r15, r1\n" \
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" mov #(0f-1f), r15\n" \
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"0: mov.l @" mem ", " old "\n"
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/* the target of mova must be 4 byte aligned, so we may need a nop */
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#define GUSA_START_ODD(mem,old) GUSA_START(mem,old,"")
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#define GUSA_START_EVEN(mem,old) GUSA_START(mem,old,"\tnop\n")
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#define GUSA_END(mem,new) \
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" mov.l " new ", @" mem "\n" \
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"1: mov r1, r15\n"
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int __sh_cas(volatile int *p, int t, int s)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_cas_llsc(p, t, s);
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if (__sh_atomic_model == SH_A_IMASK) {
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unsigned sr = mask();
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int old = *p;
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if (old==t) *p = s;
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unmask(sr);
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return old;
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}
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int old;
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__asm__ __volatile__(
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GUSA_START_EVEN("%1", "%0")
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" cmp/eq %0, %2\n"
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" bf 1f\n"
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GUSA_END("%1", "%3")
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: "=&r"(old) : "r"(p), "r"(t), "r"(s) : GUSA_CLOBBERS, "t");
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return old;
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}
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int __sh_swap(volatile int *x, int v)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_swap_llsc(x, v);
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if (__sh_atomic_model == SH_A_IMASK) {
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unsigned sr = mask();
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int old = *x;
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*x = v;
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unmask(sr);
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return old;
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}
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int old;
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__asm__ __volatile__(
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GUSA_START_EVEN("%1", "%0")
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GUSA_END("%1", "%2")
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: "=&r"(old) : "r"(x), "r"(v) : GUSA_CLOBBERS);
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return old;
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}
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int __sh_fetch_add(volatile int *x, int v)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_fetch_add_llsc(x, v);
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if (__sh_atomic_model == SH_A_IMASK) {
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unsigned sr = mask();
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int old = *x;
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*x = old + v;
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unmask(sr);
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return old;
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}
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int old, dummy;
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__asm__ __volatile__(
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GUSA_START_EVEN("%2", "%0")
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" mov %0, %1\n"
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" add %3, %1\n"
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GUSA_END("%2", "%1")
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: "=&r"(old), "=&r"(dummy) : "r"(x), "r"(v) : GUSA_CLOBBERS);
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return old;
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}
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void __sh_store(volatile int *p, int x)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_store_llsc(p, x);
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__asm__ __volatile__(
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" mov.l %1, @%0\n"
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: : "r"(p), "r"(x) : "memory");
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}
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void __sh_and(volatile int *x, int v)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_and_llsc(x, v);
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if (__sh_atomic_model == SH_A_IMASK) {
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unsigned sr = mask();
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int old = *x;
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*x = old & v;
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unmask(sr);
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return;
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}
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int dummy;
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__asm__ __volatile__(
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GUSA_START_ODD("%1", "%0")
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" and %2, %0\n"
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GUSA_END("%1", "%0")
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: "=&r"(dummy) : "r"(x), "r"(v) : GUSA_CLOBBERS);
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}
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void __sh_or(volatile int *x, int v)
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{
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if (__sh_atomic_model == SH_A_LLSC) return __sh_or_llsc(x, v);
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if (__sh_atomic_model == SH_A_IMASK) {
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unsigned sr = mask();
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int old = *x;
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*x = old | v;
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unmask(sr);
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return;
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}
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int dummy;
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__asm__ __volatile__(
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GUSA_START_ODD("%1", "%0")
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" or %2, %0\n"
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GUSA_END("%1", "%0")
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: "=&r"(dummy) : "r"(x), "r"(v) : GUSA_CLOBBERS);
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}
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#endif
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@ -1,15 +0,0 @@
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#ifndef _SH_ATOMIC_H
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#define _SH_ATOMIC_H
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#define SH_A_GUSA 0
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#define SH_A_LLSC 1
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#define SH_A_CAS 2
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#if !defined(__SH3__) && !defined(__SH4__)
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#define SH_A_IMASK 3
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#else
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#define SH_A_IMASK -1LL /* unmatchable by unsigned int */
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#endif
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extern __attribute__((__visibility__("hidden"))) unsigned __sh_atomic_model;
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#endif
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@ -1,34 +1,40 @@
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#include "pthread_impl.h"
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#include "libc.h"
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#include "sh_atomic.h"
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#include <elf.h>
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/* Also perform sh-specific init */
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#define CPU_HAS_LLSC 0x0040
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#define CPU_HAS_CAS_L 0x0400
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__attribute__((__visibility__("hidden"))) unsigned __sh_atomic_model, __sh_nommu;
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__attribute__((__visibility__("hidden")))
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extern const char __sh_cas_gusa[], __sh_cas_llsc[], __sh_cas_imask[], __sh_cas_cas_l[];
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__attribute__((__visibility__("hidden")))
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const void *__sh_cas_ptr;
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__attribute__((__visibility__("hidden")))
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unsigned __sh_nommu;
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int __set_thread_area(void *p)
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{
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size_t *aux;
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__asm__ __volatile__ ( "ldc %0, gbr" : : "r"(p) : "memory" );
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#ifndef __SH4A__
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if (__hwcap & CPU_HAS_LLSC) {
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__sh_atomic_model = SH_A_LLSC;
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return 0;
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}
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__sh_cas_ptr = __sh_cas_gusa;
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#if !defined(__SH3__) && !defined(__SH4__)
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for (aux=libc.auxv; *aux; aux+=2) {
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if (*aux != AT_PLATFORM) continue;
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const char *s = (void *)aux[1];
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if (s[0]!='s' || s[1]!='h' || s[2]!='2' || s[3]-'0'<10u) break;
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__sh_atomic_model = SH_A_IMASK;
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__sh_cas_ptr = __sh_cas_imask;
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__sh_nommu = 1;
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return 0;
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}
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#endif
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/* __sh_atomic_model = SH_A_GUSA; */ /* 0, default */
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if (__hwcap & CPU_HAS_CAS_L)
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__sh_cas_ptr = __sh_cas_cas_l;
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else if (__hwcap & CPU_HAS_LLSC)
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__sh_cas_ptr = __sh_cas_llsc;
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#endif
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return 0;
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}
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@ -0,0 +1,65 @@
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/* Contract for all versions is same as cas.l r2,r3,@r0
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* pr and r1 are also clobbered (by jsr & r1 as temp).
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* r0,r2,r4-r15 must be preserved.
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* r3 contains result (==r2 iff cas succeeded). */
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.align 2
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.global __sh_cas_gusa
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.hidden __sh_cas_gusa
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__sh_cas_gusa:
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mov.l r5,@-r15
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mov.l r4,@-r15
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mov r0,r4
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mova 1f,r0
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mov r15,r1
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mov #(0f-1f),r15
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0: mov.l @r4,r5
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cmp/eq r5,r2
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bf 1f
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mov.l r3,@r4
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1: mov r1,r15
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mov r5,r3
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mov r4,r0
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mov.l @r15+,r4
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rts
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mov.l @r15+,r5
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.global __sh_cas_llsc
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.hidden __sh_cas_llsc
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__sh_cas_llsc:
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mov r0,r1
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synco
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0: movli.l @r1,r0
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cmp/eq r0,r2
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bf 1f
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mov r3,r0
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movco.l r0,@r1
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bf 0b
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mov r2,r0
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1: synco
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mov r0,r3
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rts
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mov r1,r0
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.global __sh_cas_imask
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.hidden __sh_cas_imask
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__sh_cas_imask:
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mov r0,r1
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stc sr,r0
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mov.l r0,@-r15
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or #0xf0,r0
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ldc r0,sr
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mov.l @r1,r0
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cmp/eq r0,r2
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bf 1f
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mov.l r3,@r1
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1: ldc.l @r15+,sr
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mov r0,r3
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rts
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mov r1,r0
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.global __sh_cas_cas_l
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.hidden __sh_cas_cas_l
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__sh_cas_cas_l:
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rts
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.word 0x2323 /* cas.l r2,r3,@r0 */
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