From 407aea628af8c81d9e3f5a068568f2217db71bba Mon Sep 17 00:00:00 2001
From: Rich Felker <dalias@aerifal.cx>
Date: Sat, 3 Feb 2024 19:59:26 -0500
Subject: [PATCH] riscv: add TLSDESC support

---
 arch/riscv64/reloc.h       |  1 +
 src/ldso/riscv64/tlsdesc.s | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)
 create mode 100644 src/ldso/riscv64/tlsdesc.s

diff --git a/arch/riscv64/reloc.h b/arch/riscv64/reloc.h
index 1ca13811..7c7c0611 100644
--- a/arch/riscv64/reloc.h
+++ b/arch/riscv64/reloc.h
@@ -17,6 +17,7 @@
 #define REL_DTPMOD      R_RISCV_TLS_DTPMOD64
 #define REL_DTPOFF      R_RISCV_TLS_DTPREL64
 #define REL_TPOFF       R_RISCV_TLS_TPREL64
+#define REL_TLSDESC     R_RISCV_TLSDESC
 
 #define CRTJMP(pc,sp) __asm__ __volatile__( \
 	"mv sp, %1 ; jr %0" : : "r"(pc), "r"(sp) : "memory" )
diff --git a/src/ldso/riscv64/tlsdesc.s b/src/ldso/riscv64/tlsdesc.s
new file mode 100644
index 00000000..bef8b322
--- /dev/null
+++ b/src/ldso/riscv64/tlsdesc.s
@@ -0,0 +1,32 @@
+.text
+.global __tlsdesc_static
+.hidden __tlsdesc_static
+.type __tlsdesc_static,%function
+__tlsdesc_static:
+	ld a0,8(a0)
+	jr t0
+
+.global __tlsdesc_dynamic
+.hidden __tlsdesc_dynamic
+.type __tlsdesc_dynamic,%function
+__tlsdesc_dynamic:
+	add sp,sp,-16
+	sd t1,(sp)
+	sd t2,8(sp)
+
+	ld t2,-8(tp) # t2=dtv
+
+	ld a0,8(a0)  # a0=&{modidx,off}
+	ld t1,8(a0)  # t1=off
+	ld a0,(a0)   # a0=modidx
+	sll a0,a0,3  # a0=8*modidx
+
+	add a0,a0,t2 # a0=dtv+8*modidx
+	ld a0,(a0)   # a0=dtv[modidx]
+	add a0,a0,t1 # a0=dtv[modidx]+off
+	sub a0,a0,tp # a0=dtv[modidx]+off-tp
+
+	ld t1,(sp)
+	ld t2,8(sp)
+	add sp,sp,16
+	jr t0