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use dmb barrier instruction for atomics on arm v7 

aside from potentially offering better performance, this change is
needed since the old coprocessor-based approach to barriers is
deprecated in arm v7, and some compilers/assemblers issue errors when
using the deprecated instruction for v7 targets.
This commit is contained in:
Rich Felker 2014-04-14 23:41:49 -04:00
parent 83c98aac4c
commit 3933fdd500
1 changed files with 9 additions and 2 deletions
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11
arch/arm/atomic.h
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@ -25,17 +25,24 @@ static inline int a_ctz_64(uint64_t x)
#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \ #if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
|| __ARM_ARCH >= 7 || __ARM_ARCH >= 7
#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
#define MEM_BARRIER "dmb ish"
#else
#define MEM_BARRIER "mcr p15,0,r0,c7,c10,5"
#endif
static inline int __k_cas(int t, int s, volatile int *p) static inline int __k_cas(int t, int s, volatile int *p)
{ {
int ret; int ret;
__asm__( __asm__(
" mcr p15,0,r0,c7,c10,5\n" " " MEM_BARRIER "\n"
"1: ldrex %0,%3\n" "1: ldrex %0,%3\n"
" subs %0,%0,%1\n" " subs %0,%0,%1\n"
" strexeq %0,%2,%3\n" " strexeq %0,%2,%3\n"
" teqeq %0,#1\n" " teqeq %0,#1\n"
" beq 1b\n" " beq 1b\n"
" mcr p15,0,r0,c7,c10,5\n" " " MEM_BARRIER "\n"
: "=&r"(ret) : "=&r"(ret)
: "r"(t), "r"(s), "Q"(*p) : "r"(t), "r"(s), "Q"(*p)
: "memory", "cc" ); : "memory", "cc" );