mirror of git://git.musl-libc.org/musl
use dmb barrier instruction for atomics on arm v7
aside from potentially offering better performance, this change is needed since the old coprocessor-based approach to barriers is deprecated in arm v7, and some compilers/assemblers issue errors when using the deprecated instruction for v7 targets.
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@ -25,17 +25,24 @@ static inline int a_ctz_64(uint64_t x)
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#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
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#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
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|| __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
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|| __ARM_ARCH >= 7
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|| __ARM_ARCH >= 7
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#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define MEM_BARRIER "dmb ish"
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#else
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#define MEM_BARRIER "mcr p15,0,r0,c7,c10,5"
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#endif
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static inline int __k_cas(int t, int s, volatile int *p)
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static inline int __k_cas(int t, int s, volatile int *p)
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{
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{
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int ret;
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int ret;
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__asm__(
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__asm__(
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" mcr p15,0,r0,c7,c10,5\n"
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" " MEM_BARRIER "\n"
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"1: ldrex %0,%3\n"
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"1: ldrex %0,%3\n"
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" subs %0,%0,%1\n"
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" subs %0,%0,%1\n"
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" strexeq %0,%2,%3\n"
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" strexeq %0,%2,%3\n"
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" teqeq %0,#1\n"
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" teqeq %0,#1\n"
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" beq 1b\n"
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" beq 1b\n"
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" mcr p15,0,r0,c7,c10,5\n"
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" " MEM_BARRIER "\n"
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: "=&r"(ret)
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: "=&r"(ret)
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: "r"(t), "r"(s), "Q"(*p)
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: "r"(t), "r"(s), "Q"(*p)
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: "memory", "cc" );
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: "memory", "cc" );
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