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fix aarch64 atomics to load/store 32bit only

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a_ll/a_sc inline asm used 64bit register operands (%0) instead of 32bit
ones (%w0), this at least broke a_and_64 (which always cleared the top
32bit, leaking memory in malloc).
This commit is contained in:
Szabolcs Nagy 2016-01-24 20:51:34 +00:00 committed by Rich Felker
parent b17fbd3520
commit 2d14fa39b0
1 changed files with 2 additions and 2 deletions
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4
arch/aarch64/atomic_arch.h
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@ -2,7 +2,7 @@
static inline int a_ll(volatile int *p)
{
int v;
__asm__ __volatile__ ("ldaxr %0, %1" : "=r"(v) : "Q"(*p));
__asm__ __volatile__ ("ldaxr %w0,%1" : "=r"(v) : "Q"(*p));
return v;
}
@ -10,7 +10,7 @@ static inline int a_ll(volatile int *p)
static inline int a_sc(volatile int *p, int v)
{
int r;
__asm__ __volatile__ ("stlxr %w0,%1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
__asm__ __volatile__ ("stlxr %w0,%w1,%2" : "=&r"(r) : "r"(v), "Q"(*p) : "memory");
return !r;
}