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mpv/cpudetect.h
gpoirier 928e4433aa Add detection of x86 CPU features SSSE3 and SSE4a.
Patch by Zhou, Zongyi %zz65 A cornell P edu%
Original thread:
date: Wed, Nov 19, 2008 at 4:22 PM
subject: Re: [MPlayer-dev-eng] [PATCH] yadif SSE2/SSSE3 optimization


git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@27960 b3059339-0415-0410-9bf9-f77b7e298cf2
2008-11-19 16:41:59 +00:00

63 lines
1.2 KiB
C

#ifndef MPLAYER_CPUDETECT_H
#define MPLAYER_CPUDETECT_H
#define CPUTYPE_I386 3
#define CPUTYPE_I486 4
#define CPUTYPE_I586 5
#define CPUTYPE_I686 6
#ifdef ARCH_X86_64
# define REGa rax
# define REGb rbx
# define REGBP rbp
# define REGSP rsp
# define REG_a "rax"
# define REG_b "rbx"
# define REG_c "rcx"
# define REG_d "rdx"
# define REG_S "rsi"
# define REG_D "rdi"
# define REG_SP "rsp"
# define REG_BP "rbp"
#else
# define REGa eax
# define REGb ebx
# define REGBP ebp
# define REGSP esp
# define REG_a "eax"
# define REG_b "ebx"
# define REG_c "ecx"
# define REG_d "edx"
# define REG_S "esi"
# define REG_D "edi"
# define REG_SP "esp"
# define REG_BP "ebp"
#endif
typedef struct cpucaps_s {
int cpuType;
int cpuModel;
int cpuStepping;
int hasMMX;
int hasMMX2;
int has3DNow;
int has3DNowExt;
int hasSSE;
int hasSSE2;
int hasSSSE3;
int hasSSE4a;
int isX86;
unsigned cl_size; /* size of cache line */
int hasAltiVec;
int hasTSC;
} CpuCaps;
extern CpuCaps gCpuCaps;
void GetCpuCaps(CpuCaps *caps);
/* returned value is malloc()'ed so free() it after use */
char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]);
#endif /* MPLAYER_CPUDETECT_H */