mirror of
https://github.com/mpv-player/mpv
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aab77fd7ec
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@106 b3059339-0415-0410-9bf9-f77b7e298cf2
947 lines
24 KiB
C
947 lines
24 KiB
C
// YUY2 support (see config.format) added by A'rpi/ESP-team
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// double buffering added by A'rpi/ESP-team
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// Set this value, if autodetection fails! (video ram size in megabytes)
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// #define MGA_MEMORY_SIZE 16
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//#define MGA_ALLOW_IRQ
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#define MGA_VSYNC_POS 2
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/*
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*
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* mga_vid.c
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*
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* Copyright (C) 1999 Aaron Holtzman
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*
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* Module skeleton based on gutted agpgart module by Jeff Hartmann
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* <slicer@ionet.net>
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*
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* Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0
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*
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* BES == Back End Scaler
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*
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* This software has been released under the terms of the GNU Public
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* license. See http://www.gnu.org/copyleft/gpl.html for details.
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*/
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//It's entirely possible this major conflicts with something else
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/* mknod /dev/mga_vid c 178 0 */
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#include <linux/config.h>
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/malloc.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include "mga_vid.h"
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#ifdef CONFIG_MTRR
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#include <asm/mtrr.h>
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#endif
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#define TRUE 1
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#define FALSE 0
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#define MGA_VID_MAJOR 178
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//#define MGA_VIDMEM_SIZE mga_ram_size
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#ifndef PCI_DEVICE_ID_MATROX_G200_PCI
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#define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520
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#endif
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#ifndef PCI_DEVICE_ID_MATROX_G200_AGP
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#define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521
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#endif
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#ifndef PCI_DEVICE_ID_MATROX_G400
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#define PCI_DEVICE_ID_MATROX_G400 0x0525
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#endif
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MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>");
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typedef struct bes_registers_s
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{
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//BES Control
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uint32_t besctl;
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//BES Global control
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uint32_t besglobctl;
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//Luma control (brightness and contrast)
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uint32_t beslumactl;
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//Line pitch
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uint32_t bespitch;
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//Buffer A-1 Chroma 3 plane org
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uint32_t besa1c3org;
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//Buffer A-1 Chroma org
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uint32_t besa1corg;
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//Buffer A-1 Luma org
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uint32_t besa1org;
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//Buffer A-2 Chroma 3 plane org
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uint32_t besa2c3org;
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//Buffer A-2 Chroma org
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uint32_t besa2corg;
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//Buffer A-2 Luma org
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uint32_t besa2org;
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//Buffer B-1 Chroma 3 plane org
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uint32_t besb1c3org;
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//Buffer B-1 Chroma org
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uint32_t besb1corg;
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//Buffer B-1 Luma org
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uint32_t besb1org;
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//Buffer B-2 Chroma 3 plane org
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uint32_t besb2c3org;
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//Buffer B-2 Chroma org
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uint32_t besb2corg;
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//Buffer B-2 Luma org
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uint32_t besb2org;
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//BES Horizontal coord
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uint32_t beshcoord;
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//BES Horizontal inverse scaling [5.14]
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uint32_t beshiscal;
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//BES Horizontal source start [10.14] (for scaling)
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uint32_t beshsrcst;
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//BES Horizontal source ending [10.14] (for scaling)
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uint32_t beshsrcend;
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//BES Horizontal source last
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uint32_t beshsrclst;
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//BES Vertical coord
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uint32_t besvcoord;
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//BES Vertical inverse scaling [5.14]
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uint32_t besviscal;
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//BES Field 1 vertical source last position
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uint32_t besv1srclst;
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//BES Field 1 weight start
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uint32_t besv1wght;
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//BES Field 2 vertical source last position
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uint32_t besv2srclst;
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//BES Field 2 weight start
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uint32_t besv2wght;
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} bes_registers_t;
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static bes_registers_t regs;
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static uint32_t mga_vid_in_use = 0;
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static uint32_t is_g400 = 0;
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static uint32_t vid_src_ready = 0;
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static uint32_t vid_overlay_on = 0;
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static uint8_t *mga_mmio_base = 0;
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static uint32_t mga_mem_base = 0;
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static int mga_src_base = 0; // YUV buffer position in video memory
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static uint32_t mga_ram_size = 0; // how much megabytes videoram we have
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//static int mga_force_memsize = 0;
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MODULE_PARM(mga_ram_size, "i");
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static struct pci_dev *pci_dev;
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static mga_vid_config_t mga_config;
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static int mga_irq = -1;
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//All register offsets are converted to word aligned offsets (32 bit)
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//because we want all our register accesses to be 32 bits
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#define VCOUNT 0x1e20
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#define PALWTADD 0x3c00 // Index register for X_DATAREG port
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#define X_DATAREG 0x3c0a
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#define XMULCTRL 0x19
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#define BPP_8 0x00
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#define BPP_15 0x01
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#define BPP_16 0x02
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#define BPP_24 0x03
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#define BPP_32_DIR 0x04
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#define BPP_32_PAL 0x07
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#define XCOLMSK 0x40
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#define X_COLKEY 0x42
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#define XKEYOPMODE 0x51
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#define XCOLMSK0RED 0x52
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#define XCOLMSK0GREEN 0x53
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#define XCOLMSK0BLUE 0x54
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#define XCOLKEY0RED 0x55
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#define XCOLKEY0GREEN 0x56
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#define XCOLKEY0BLUE 0x57
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// Backend Scaler registers
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#define BESCTL 0x3d20
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#define BESGLOBCTL 0x3dc0
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#define BESLUMACTL 0x3d40
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#define BESPITCH 0x3d24
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#define BESA1C3ORG 0x3d60
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#define BESA1CORG 0x3d10
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#define BESA1ORG 0x3d00
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#define BESA2C3ORG 0x3d64
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#define BESA2CORG 0x3d14
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#define BESA2ORG 0x3d04
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#define BESB1C3ORG 0x3d68
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#define BESB1CORG 0x3d18
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#define BESB1ORG 0x3d08
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#define BESB2C3ORG 0x3d6C
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#define BESB2CORG 0x3d1C
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#define BESB2ORG 0x3d0C
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#define BESHCOORD 0x3d28
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#define BESHISCAL 0x3d30
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#define BESHSRCEND 0x3d3C
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#define BESHSRCLST 0x3d50
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#define BESHSRCST 0x3d38
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#define BESV1WGHT 0x3d48
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#define BESV2WGHT 0x3d4c
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#define BESV1SRCLST 0x3d54
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#define BESV2SRCLST 0x3d58
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#define BESVISCAL 0x3d34
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#define BESVCOORD 0x3d2c
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#define BESSTATUS 0x3dc4
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#define CRTCX 0x1fd4
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#define CRTCD 0x1fd5
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#define IEN 0x1e1c
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#define ICLEAR 0x1e18
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#define STATUS 0x1e14
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static int mga_next_frame=0;
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static void mga_vid_frame_sel(int frame)
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{
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if ( mga_irq != -1 ) {
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mga_next_frame=frame;
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} else {
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//we don't need the vcount protection as we're only hitting
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//one register (and it doesn't seem to be double buffered)
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regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25);
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writel( regs.besctl, mga_mmio_base + BESCTL );
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// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
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mga_mmio_base + BESGLOBCTL);
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}
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}
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static void mga_vid_write_regs(void)
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{
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//Make sure internal registers don't get updated until we're done
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writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
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mga_mmio_base + BESGLOBCTL);
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// color or coordinate keying
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writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
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writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG);
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if ( mga_config.colkey_on )
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{
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uint32_t r=0, g=0, b=0;
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writeb( XMULCTRL, mga_mmio_base + PALWTADD);
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switch (readb (mga_mmio_base + X_DATAREG))
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{
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case BPP_8:
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/* Need to look up the color index, just using
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color 0 for now. */
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break;
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case BPP_15:
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r = mga_config.colkey_red >> 3;
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g = mga_config.colkey_green >> 3;
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b = mga_config.colkey_blue >> 3;
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break;
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case BPP_16:
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r = mga_config.colkey_red >> 3;
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g = mga_config.colkey_green >> 2;
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b = mga_config.colkey_blue >> 3;
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break;
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case BPP_24:
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case BPP_32_DIR:
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case BPP_32_PAL:
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r = mga_config.colkey_red;
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g = mga_config.colkey_green;
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b = mga_config.colkey_blue;
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break;
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}
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// Disable color keying on alpha channel
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writeb( XCOLMSK, mga_mmio_base + PALWTADD);
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writeb( 0x00, mga_mmio_base + X_DATAREG);
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writeb( X_COLKEY, mga_mmio_base + PALWTADD);
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writeb( 0x00, mga_mmio_base + X_DATAREG);
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// Set up color key registers
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writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
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writeb( r, mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
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writeb( g, mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
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writeb( b, mga_mmio_base + X_DATAREG);
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// Set up color key mask registers
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writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
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writeb( 0xff, mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
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writeb( 0xff, mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
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writeb( 0xff, mga_mmio_base + X_DATAREG);
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}
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// Backend Scaler
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writel( regs.besctl, mga_mmio_base + BESCTL);
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if(is_g400)
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writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
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writel( regs.bespitch, mga_mmio_base + BESPITCH);
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writel( regs.besa1org, mga_mmio_base + BESA1ORG);
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writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
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writel( regs.besa2org, mga_mmio_base + BESA2ORG);
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writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
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writel( regs.besb1org, mga_mmio_base + BESB1ORG);
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writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
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writel( regs.besb2org, mga_mmio_base + BESB2ORG);
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writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
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if(is_g400)
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{
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writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
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writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
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writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
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writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
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}
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writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
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writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
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writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
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writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
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writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
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writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
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writel( regs.besviscal, mga_mmio_base + BESVISCAL);
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writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
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writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
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writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
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writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
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//update the registers somewhere between 1 and 2 frames from now.
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writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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mga_mmio_base + BESGLOBCTL);
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#if 0
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printk(KERN_DEBUG "mga_vid: wrote BES registers\n");
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printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n",
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readl(mga_mmio_base + BESCTL));
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printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n",
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readl(mga_mmio_base + BESGLOBCTL));
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printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n",
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readl(mga_mmio_base + BESSTATUS));
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#endif
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}
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static int mga_vid_set_config(mga_vid_config_t *config)
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{
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int x, y, sw, sh, dw, dh;
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int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
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int frame_size=config->frame_size;
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x = config->x_org;
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y = config->y_org;
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sw = config->src_width;
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sh = config->src_height;
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dw = config->dest_width;
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dh = config->dest_height;
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printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n",
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dw, dh, x, y, sw, sh, config->format);
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//FIXME check that window is valid and inside desktop
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//FIXME figure out a better way to allocate memory on card
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//allocate 2 megs
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//mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000;
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//mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000;
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//Setup the BES registers for a three plane 4:2:0 video source
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switch(config->format){
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case MGA_VID_FORMAT_YV12:
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regs.besctl = 1 // BES enabled
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+ (0<<6) // even start polarity
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+ (1<<10) // x filtering enabled
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+ (1<<11) // y filtering enabled
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+ (1<<16) // chroma upsampling
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+ (1<<17) // 4:2:0 mode
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+ (1<<18); // dither enabled
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if(is_g400)
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{
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//zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
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//disabled, rgb mode disabled
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regs.besglobctl = (1<<5);
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}
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else
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{
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//zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
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//in 1357, BES register update on besvcnt
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regs.besglobctl = 0;
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}
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break;
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case MGA_VID_FORMAT_YUY2:
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regs.besctl = 1 // BES enabled
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+ (0<<6) // even start polarity
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+ (1<<10) // x filtering enabled
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+ (1<<11) // y filtering enabled
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+ (1<<16) // chroma upsampling
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+ (0<<17) // 4:2:2 mode
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+ (1<<18); // dither enabled
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regs.besglobctl = 0; // YUY2 format selected
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break;
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default:
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printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format);
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return -1;
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}
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//Disable contrast and brightness control
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regs.besglobctl = (1<<5) + (1<<7);
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regs.beslumactl = (0x7f << 16) + (0x80<<0);
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regs.beslumactl = 0x80<<0;
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//Setup destination window boundaries
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besleft = x > 0 ? x : 0;
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bestop = y > 0 ? y : 0;
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regs.beshcoord = (besleft<<16) + (x + dw-1);
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regs.besvcoord = (bestop<<16) + (y + dh-1);
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//Setup source dimensions
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regs.beshsrclst = (sw - 1) << 16;
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regs.bespitch = (sw + 31) & ~31 ;
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//Setup horizontal scaling
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ifactor = ((sw-1)<<14)/(dw-1);
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ofsleft = besleft - x;
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regs.beshiscal = ifactor<<2;
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regs.beshsrcst = (ofsleft*ifactor)<<2;
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regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
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|
|
//Setup vertical scaling
|
|
ifactor = ((sh-1)<<14)/(dh-1);
|
|
ofstop = bestop - y;
|
|
|
|
regs.besviscal = ifactor<<2;
|
|
|
|
baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
|
|
//frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
|
|
regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
|
|
regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size;
|
|
regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size;
|
|
regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size;
|
|
|
|
if(config->format==MGA_VID_FORMAT_YV12){
|
|
// planar YUV frames:
|
|
if (is_g400)
|
|
baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
|
|
else
|
|
baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
|
|
|
|
regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
|
|
regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh;
|
|
regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh;
|
|
regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh;
|
|
regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
|
|
regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
|
|
regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
|
|
regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
|
|
}
|
|
|
|
weight = ofstop * (regs.besviscal >> 2);
|
|
weights = weight < 0 ? 1 : 0;
|
|
regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
|
|
regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
|
|
|
|
mga_vid_write_regs();
|
|
return 0;
|
|
}
|
|
|
|
#ifdef MGA_ALLOW_IRQ
|
|
|
|
static void enable_irq(){
|
|
long int cc;
|
|
|
|
cc = readl(mga_mmio_base + IEN);
|
|
// printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff));
|
|
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
|
|
writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
|
|
writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
|
|
|
|
writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
|
|
|
|
}
|
|
|
|
static void disable_irq(){
|
|
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
|
|
}
|
|
|
|
void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) {
|
|
// static int frame=0;
|
|
static int counter=0;
|
|
long int cc;
|
|
// if ( ! mga_enabled_flag ) return;
|
|
|
|
// printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
|
|
|
|
//printk("mga_interrupt #%d\n", irq);
|
|
|
|
if ( irq != -1 ) {
|
|
|
|
cc = readl(mga_mmio_base + STATUS);
|
|
if ( ! (cc & 0x10) ) return; /* vsyncpen */
|
|
// debug_irqcnt++;
|
|
}
|
|
|
|
// if ( debug_irqignore ) {
|
|
// debug_irqignore = 0;
|
|
|
|
|
|
/*
|
|
if ( mga_conf_deinterlace ) {
|
|
if ( mga_first_field ) {
|
|
// printk("mga_interrupt first field\n");
|
|
if ( syncfb_interrupt() )
|
|
mga_first_field = 0;
|
|
} else {
|
|
// printk("mga_interrupt second field\n");
|
|
mga_select_buffer( mga_current_field | 2 );
|
|
mga_first_field = 1;
|
|
}
|
|
} else {
|
|
syncfb_interrupt();
|
|
}
|
|
*/
|
|
|
|
// frame=(frame+1)&1;
|
|
regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
|
|
writel( regs.besctl, mga_mmio_base + BESCTL );
|
|
|
|
#if 0
|
|
++counter;
|
|
if(!(counter&63)){
|
|
printk("mga irq counter = %d\n",counter);
|
|
}
|
|
#endif
|
|
|
|
// } else {
|
|
// debug_irqignore = 1;
|
|
// }
|
|
|
|
if ( irq != -1 ) {
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
writeb( 0, mga_mmio_base + CRTCD );
|
|
writeb( 0x10, mga_mmio_base + CRTCD );
|
|
}
|
|
|
|
// writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL);
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
|
|
{
|
|
int frame;
|
|
|
|
switch(cmd)
|
|
{
|
|
case MGA_VID_CONFIG:
|
|
//FIXME remove
|
|
// printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT));
|
|
printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base);
|
|
printk(KERN_DEBUG "mga_mem_base = %08lx\n",mga_mem_base);
|
|
//FIXME remove
|
|
|
|
printk(KERN_DEBUG "mga_vid: Received configuration\n");
|
|
|
|
if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
|
|
{
|
|
printk(KERN_ERR "mga_vid: failed copy from userspace\n");
|
|
return(-EFAULT);
|
|
}
|
|
if(mga_config.version != MGA_VID_VERSION){
|
|
printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version);
|
|
return(-EFAULT);
|
|
}
|
|
|
|
if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){
|
|
printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size);
|
|
return(-EFAULT);
|
|
}
|
|
|
|
if(mga_config.num_frames<1 || mga_config.num_frames>4){
|
|
printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames);
|
|
return(-EFAULT);
|
|
}
|
|
|
|
mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size);
|
|
if(mga_src_base<0){
|
|
printk(KERN_ERR "mga_vid: not enough memory for frames!\n");
|
|
return(-EFAULT);
|
|
}
|
|
mga_src_base &= (~0xFFFF); // 64k boundary
|
|
printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base);
|
|
|
|
if (is_g400)
|
|
mga_config.card_type = MGA_G400;
|
|
else
|
|
mga_config.card_type = MGA_G200;
|
|
|
|
mga_config.ram_size = mga_ram_size;
|
|
|
|
if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t)))
|
|
{
|
|
printk(KERN_ERR "mga_vid: failed copy to userspace\n");
|
|
return(-EFAULT);
|
|
}
|
|
return mga_vid_set_config(&mga_config);
|
|
break;
|
|
|
|
case MGA_VID_ON:
|
|
printk(KERN_DEBUG "mga_vid: Video ON\n");
|
|
vid_src_ready = 1;
|
|
if(vid_overlay_on)
|
|
{
|
|
regs.besctl |= 1;
|
|
mga_vid_write_regs();
|
|
}
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if ( mga_irq != -1 ) enable_irq();
|
|
#endif
|
|
mga_next_frame=0;
|
|
break;
|
|
|
|
case MGA_VID_OFF:
|
|
printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n");
|
|
vid_src_ready = 0;
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if ( mga_irq != -1 ) disable_irq();
|
|
#endif
|
|
regs.besctl &= ~1;
|
|
mga_vid_write_regs();
|
|
break;
|
|
|
|
case MGA_VID_FSEL:
|
|
if(copy_from_user(&frame,(int *) arg,sizeof(int)))
|
|
{
|
|
printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n");
|
|
return(-EFAULT);
|
|
}
|
|
|
|
mga_vid_frame_sel(frame);
|
|
break;
|
|
|
|
default:
|
|
printk(KERN_ERR "mga_vid: Invalid ioctl\n");
|
|
return (-EINVAL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int mga_vid_find_card(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
unsigned int card_option, temp;
|
|
|
|
if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL)))
|
|
{
|
|
is_g400 = 1;
|
|
printk(KERN_INFO "mga_vid: Found MGA G400/G450\n");
|
|
}
|
|
else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL)))
|
|
{
|
|
is_g400 = 0;
|
|
printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n");
|
|
}
|
|
else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL)))
|
|
{
|
|
is_g400 = 0;
|
|
printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n");
|
|
}
|
|
else
|
|
{
|
|
printk(KERN_ERR "mga_vid: No supported cards found\n");
|
|
return FALSE;
|
|
}
|
|
|
|
pci_dev = dev;
|
|
|
|
mga_irq = pci_dev->irq;
|
|
|
|
#if LINUX_VERSION_CODE >= 0x020300
|
|
mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000);
|
|
mga_mem_base = dev->resource[0].start;
|
|
#else
|
|
mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000);
|
|
mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK;
|
|
#endif
|
|
printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08lX\n", mga_mmio_base, mga_irq, mga_mem_base);
|
|
|
|
pci_read_config_dword(dev, 0x40, &card_option);
|
|
printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
|
|
(card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
|
|
|
|
// temp = (card_option >> 10) & 0x17;
|
|
|
|
if (mga_ram_size) {
|
|
printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size);
|
|
} else {
|
|
|
|
#ifdef MGA_MEMORY_SIZE
|
|
mga_ram_size = MGA_MEMORY_SIZE;
|
|
printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
|
|
|
#else
|
|
|
|
if (is_g400){
|
|
switch((card_option>>10)&0x17){
|
|
// SDRAM:
|
|
case 0x00:
|
|
case 0x04: mga_ram_size = 16; break;
|
|
case 0x03: mga_ram_size = 32; break;
|
|
// SGRAM:
|
|
case 0x10:
|
|
case 0x14: mga_ram_size = 32; break;
|
|
case 0x11:
|
|
case 0x12: mga_ram_size = 16; break;
|
|
default:
|
|
mga_ram_size = 16;
|
|
printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!");
|
|
}
|
|
}else{
|
|
switch((card_option>>11)&1){
|
|
case 0: mga_ram_size = 8; break;
|
|
default: mga_ram_size = 16;
|
|
}
|
|
}
|
|
#if 0
|
|
// printk("List resources -----------\n");
|
|
for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
|
|
struct resource *res=&pci_dev->resource[temp];
|
|
if(res->flags){
|
|
int size=(1+res->end-res->start)>>20;
|
|
printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
|
|
if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
|
|
if(size>mga_ram_size && size<=64) mga_ram_size=size;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
|
#endif
|
|
}
|
|
|
|
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if ( mga_irq != -1 ) {
|
|
int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
|
|
if ( tmp ) {
|
|
printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
|
|
mga_irq=-1;
|
|
} else {
|
|
printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq);
|
|
}
|
|
} else {
|
|
printk(KERN_INFO "syncfb (mga): No valid irq was found\n");
|
|
mga_irq=-1;
|
|
}
|
|
#else
|
|
printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n");
|
|
mga_irq=-1;
|
|
#endif
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma)
|
|
{
|
|
|
|
printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n");
|
|
if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base,
|
|
vma->vm_end - vma->vm_start, vma->vm_page_prot))
|
|
{
|
|
printk(KERN_ERR "mga_vid: error mapping video memory\n");
|
|
return(-EAGAIN);
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int mga_vid_release(struct inode *inode, struct file *file)
|
|
{
|
|
//Close the window just in case
|
|
printk(KERN_DEBUG "mga_vid: Video OFF (release)\n");
|
|
|
|
vid_src_ready = 0;
|
|
regs.besctl &= ~1;
|
|
mga_vid_write_regs();
|
|
mga_vid_in_use = 0;
|
|
|
|
MOD_DEC_USE_COUNT;
|
|
return 0;
|
|
}
|
|
|
|
static long long mga_vid_lseek(struct file *file, long long offset, int origin)
|
|
{
|
|
return -ESPIPE;
|
|
}
|
|
|
|
static int mga_vid_open(struct inode *inode, struct file *file)
|
|
{
|
|
int minor = MINOR(inode->i_rdev);
|
|
|
|
if(minor != 0)
|
|
return(-ENXIO);
|
|
|
|
if(mga_vid_in_use == 1)
|
|
return(-EBUSY);
|
|
|
|
mga_vid_in_use = 1;
|
|
MOD_INC_USE_COUNT;
|
|
return(0);
|
|
}
|
|
|
|
#if LINUX_VERSION_CODE >= 0x020400
|
|
static struct file_operations mga_vid_fops =
|
|
{
|
|
llseek: mga_vid_lseek,
|
|
read: mga_vid_read,
|
|
write: mga_vid_write,
|
|
ioctl: mga_vid_ioctl,
|
|
mmap: mga_vid_mmap,
|
|
open: mga_vid_open,
|
|
release: mga_vid_release
|
|
};
|
|
#else
|
|
static struct file_operations mga_vid_fops =
|
|
{
|
|
mga_vid_lseek,
|
|
mga_vid_read,
|
|
mga_vid_write,
|
|
NULL,
|
|
NULL,
|
|
mga_vid_ioctl,
|
|
mga_vid_mmap,
|
|
mga_vid_open,
|
|
NULL,
|
|
mga_vid_release
|
|
};
|
|
#endif
|
|
|
|
|
|
/*
|
|
* Main Initialization Function
|
|
*/
|
|
|
|
static int mga_vid_initialize(void)
|
|
{
|
|
mga_vid_in_use = 0;
|
|
|
|
// printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n");
|
|
printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
|
|
|
|
if (mga_ram_size) {
|
|
if (mga_ram_size<4 || mga_ram_size>64) {
|
|
printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops))
|
|
{
|
|
printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR);
|
|
return -EIO;
|
|
}
|
|
|
|
if (!mga_vid_find_card())
|
|
{
|
|
printk(KERN_ERR "mga_vid: no supported devices found\n");
|
|
unregister_chrdev(MGA_VID_MAJOR, "mga_vid");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
int init_module(void)
|
|
{
|
|
return mga_vid_initialize();
|
|
}
|
|
|
|
void cleanup_module(void)
|
|
{
|
|
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if ( mga_irq != -1)
|
|
free_irq(mga_irq, &mga_irq);
|
|
#endif
|
|
|
|
if(mga_mmio_base)
|
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iounmap(mga_mmio_base);
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|
|
|
//FIXME turn off BES
|
|
printk(KERN_INFO "mga_vid: Cleaning up module\n");
|
|
unregister_chrdev(MGA_VID_MAJOR, "mga_vid");
|
|
}
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|
|