mirror of
https://github.com/mpv-player/mpv
synced 2024-12-11 17:37:23 +00:00
ded52c0bc7
(with the blessing of Rich) git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@14566 b3059339-0415-0410-9bf9-f77b7e298cf2
445 lines
12 KiB
C
445 lines
12 KiB
C
/*
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aclib - advanced C library ;)
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This file contains functions which improve and expand standard C-library
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*/
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#ifndef HAVE_SSE2
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/*
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P3 processor has only one SSE decoder so can execute only 1 sse insn per
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cpu clock, but it has 3 mmx decoders (include load/store unit)
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and executes 3 mmx insns per cpu clock.
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P4 processor has some chances, but after reading:
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http://www.emulators.com/pentium4.htm
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I have doubts. Anyway SSE2 version of this code can be written better.
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*/
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#undef HAVE_SSE
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#endif
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/*
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This part of code was taken by me from Linux-2.4.3 and slightly modified
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for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
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blocks but mplayer uses weakly ordered data and original sources can not
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speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
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>From IA-32 Intel Architecture Software Developer's Manual Volume 1,
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Order Number 245470:
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"10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
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Data referenced by a program can be temporal (data will be used again) or
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non-temporal (data will be referenced once and not reused in the immediate
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future). To make efficient use of the processor's caches, it is generally
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desirable to cache temporal data and not cache non-temporal data. Overloading
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the processor's caches with non-temporal data is sometimes referred to as
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"polluting the caches".
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The non-temporal data is written to memory with Write-Combining semantics.
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The PREFETCHh instructions permits a program to load data into the processor
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at a suggested cache level, so that it is closer to the processors load and
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store unit when it is needed. If the data is already present in a level of
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the cache hierarchy that is closer to the processor, the PREFETCHh instruction
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will not result in any data movement.
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But we should you PREFETCHNTA: Non-temporal data fetch data into location
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close to the processor, minimizing cache pollution.
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The MOVNTQ (store quadword using non-temporal hint) instruction stores
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packed integer data from an MMX register to memory, using a non-temporal hint.
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The MOVNTPS (store packed single-precision floating-point values using
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non-temporal hint) instruction stores packed floating-point data from an
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XMM register to memory, using a non-temporal hint.
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The SFENCE (Store Fence) instruction controls write ordering by creating a
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fence for memory store operations. This instruction guarantees that the results
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of every store instruction that precedes the store fence in program order is
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globally visible before any store instruction that follows the fence. The
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SFENCE instruction provides an efficient way of ensuring ordering between
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procedures that produce weakly-ordered data and procedures that consume that
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data.
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If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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*/
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// 3dnow memcpy support from kernel 2.4.2
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// by Pontscho/fresh!mindworkz
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#undef HAVE_MMX1
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#if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
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/* means: mmx v.1. Note: Since we added alignment of destinition it speedups
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of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
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standard (non MMX-optimized) version.
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Note: on K6-2+ it speedups memory copying upto 25% and
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on K7 and P3 about 500% (5 times). */
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#define HAVE_MMX1
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#endif
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#undef HAVE_K6_2PLUS
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#if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
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#define HAVE_K6_2PLUS
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#endif
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/* for small memory blocks (<256 bytes) this version is faster */
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#define small_memcpy(to,from,n)\
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{\
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register unsigned long int dummy;\
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__asm__ __volatile__(\
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"rep; movsb"\
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:"=&D"(to), "=&S"(from), "=&c"(dummy)\
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/* It's most portable way to notify compiler */\
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/* that edi, esi and ecx are clobbered in asm block. */\
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/* Thanks to A'rpi for hint!!! */\
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:"0" (to), "1" (from),"2" (n)\
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: "memory");\
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}
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#undef MMREG_SIZE
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#ifdef HAVE_SSE
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#define MMREG_SIZE 16
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#else
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#define MMREG_SIZE 64 //8
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#endif
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#undef PREFETCH
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#undef EMMS
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#ifdef HAVE_MMX2
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#define PREFETCH "prefetchnta"
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#elif defined ( HAVE_3DNOW )
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#define PREFETCH "prefetch"
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#else
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#define PREFETCH "/nop"
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#endif
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/* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
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#ifdef HAVE_3DNOW
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#define EMMS "femms"
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#else
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#define EMMS "emms"
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#endif
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#undef MOVNTQ
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#ifdef HAVE_MMX2
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#define MOVNTQ "movntq"
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#else
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#define MOVNTQ "movq"
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#endif
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#undef MIN_LEN
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#ifdef HAVE_MMX1
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#define MIN_LEN 0x800 /* 2K blocks */
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#else
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#define MIN_LEN 0x40 /* 64-byte blocks */
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#endif
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static void * RENAME(fast_memcpy)(void * to, const void * from, size_t len)
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{
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void *retval;
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size_t i;
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retval = to;
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#ifdef STATISTICS
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{
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static int freq[33];
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static int t=0;
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int i;
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for(i=0; len>(1<<i); i++);
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freq[i]++;
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t++;
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if(1024*1024*1024 % t == 0)
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for(i=0; i<32; i++)
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printf("freq < %8d %4d\n", 1<<i, freq[i]);
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}
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#endif
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#ifndef HAVE_MMX1
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/* PREFETCH has effect even for MOVSB instruction ;) */
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__asm__ __volatile__ (
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PREFETCH" (%0)\n"
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PREFETCH" 64(%0)\n"
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PREFETCH" 128(%0)\n"
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PREFETCH" 192(%0)\n"
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PREFETCH" 256(%0)\n"
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: : "r" (from) );
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#endif
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if(len >= MIN_LEN)
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{
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register unsigned long int delta;
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/* Align destinition to MMREG_SIZE -boundary */
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delta = ((unsigned long int)to)&(MMREG_SIZE-1);
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if(delta)
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{
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delta=MMREG_SIZE-delta;
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len -= delta;
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small_memcpy(to, from, delta);
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}
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i = len >> 6; /* len/64 */
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len&=63;
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/*
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This algorithm is top effective when the code consequently
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reads and writes blocks which have size of cache line.
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Size of cache line is processor-dependent.
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It will, however, be a minimum of 32 bytes on any processors.
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It would be better to have a number of instructions which
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perform reading and writing to be multiple to a number of
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processor's decoders, but it's not always possible.
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*/
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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if(((unsigned long)from) & 15)
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/* if SRC is misaligned */
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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PREFETCH" 320(%0)\n"
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"movups (%0), %%xmm0\n"
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"movups 16(%0), %%xmm1\n"
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"movups 32(%0), %%xmm2\n"
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"movups 48(%0), %%xmm3\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movntps %%xmm2, 32(%1)\n"
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"movntps %%xmm3, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from=((const unsigned char *) from)+64;
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to=((unsigned char *)to)+64;
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}
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else
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/*
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Only if SRC is aligned on 16-byte boundary.
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It allows to use movaps instead of movups, which required data
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to be aligned or a general-protection exception (#GP) is generated.
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*/
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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PREFETCH" 320(%0)\n"
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"movaps (%0), %%xmm0\n"
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"movaps 16(%0), %%xmm1\n"
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"movaps 32(%0), %%xmm2\n"
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"movaps 48(%0), %%xmm3\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movntps %%xmm2, 32(%1)\n"
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"movntps %%xmm3, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from=((const unsigned char *)from)+64;
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to=((unsigned char *)to)+64;
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}
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#else
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// Align destination at BLOCK_SIZE boundary
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for(; ((int)to & (BLOCK_SIZE-1)) && i>0; i--)
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{
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__asm__ __volatile__ (
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#ifndef HAVE_MMX1
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PREFETCH" 320(%0)\n"
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#endif
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"movq 32(%0), %%mm4\n"
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"movq 40(%0), %%mm5\n"
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"movq 48(%0), %%mm6\n"
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"movq 56(%0), %%mm7\n"
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MOVNTQ" %%mm0, (%1)\n"
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MOVNTQ" %%mm1, 8(%1)\n"
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MOVNTQ" %%mm2, 16(%1)\n"
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MOVNTQ" %%mm3, 24(%1)\n"
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MOVNTQ" %%mm4, 32(%1)\n"
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MOVNTQ" %%mm5, 40(%1)\n"
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MOVNTQ" %%mm6, 48(%1)\n"
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MOVNTQ" %%mm7, 56(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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((const unsigned char *)from)+=64;
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((unsigned char *)to)+=64;
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}
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// printf(" %d %d\n", (int)from&1023, (int)to&1023);
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// Pure Assembly cuz gcc is a bit unpredictable ;)
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if(i>=BLOCK_SIZE/64)
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asm volatile(
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"xor %%"REG_a", %%"REG_a" \n\t"
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".balign 16 \n\t"
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"1: \n\t"
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"movl (%0, %%"REG_a"), %%ebx \n\t"
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"movl 32(%0, %%"REG_a"), %%ebx \n\t"
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"movl 64(%0, %%"REG_a"), %%ebx \n\t"
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"movl 96(%0, %%"REG_a"), %%ebx \n\t"
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"add $128, %%"REG_a" \n\t"
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"cmp %3, %%"REG_a" \n\t"
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" jb 1b \n\t"
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"xor %%"REG_a", %%"REG_a" \n\t"
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".balign 16 \n\t"
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"2: \n\t"
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"movq (%0, %%"REG_a"), %%mm0\n"
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"movq 8(%0, %%"REG_a"), %%mm1\n"
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"movq 16(%0, %%"REG_a"), %%mm2\n"
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"movq 24(%0, %%"REG_a"), %%mm3\n"
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"movq 32(%0, %%"REG_a"), %%mm4\n"
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"movq 40(%0, %%"REG_a"), %%mm5\n"
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"movq 48(%0, %%"REG_a"), %%mm6\n"
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"movq 56(%0, %%"REG_a"), %%mm7\n"
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MOVNTQ" %%mm0, (%1, %%"REG_a")\n"
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MOVNTQ" %%mm1, 8(%1, %%"REG_a")\n"
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MOVNTQ" %%mm2, 16(%1, %%"REG_a")\n"
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MOVNTQ" %%mm3, 24(%1, %%"REG_a")\n"
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MOVNTQ" %%mm4, 32(%1, %%"REG_a")\n"
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MOVNTQ" %%mm5, 40(%1, %%"REG_a")\n"
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MOVNTQ" %%mm6, 48(%1, %%"REG_a")\n"
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MOVNTQ" %%mm7, 56(%1, %%"REG_a")\n"
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"add $64, %%"REG_a" \n\t"
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"cmp %3, %%"REG_a" \n\t"
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"jb 2b \n\t"
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#if CONFUSION_FACTOR > 0
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// a few percent speedup on out of order executing CPUs
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"mov %5, %%"REG_a" \n\t"
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"2: \n\t"
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"movl (%0), %%ebx \n\t"
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"movl (%0), %%ebx \n\t"
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"movl (%0), %%ebx \n\t"
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"movl (%0), %%ebx \n\t"
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"dec %%"REG_a" \n\t"
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" jnz 2b \n\t"
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#endif
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"xor %%"REG_a", %%"REG_a" \n\t"
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"add %3, %0 \n\t"
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"add %3, %1 \n\t"
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"sub %4, %2 \n\t"
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"cmp %4, %2 \n\t"
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" jae 1b \n\t"
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: "+r" (from), "+r" (to), "+r" (i)
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: "r" ((long)BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" ((long)CONFUSION_FACTOR)
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: "%"REG_a, "%ebx"
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);
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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#ifndef HAVE_MMX1
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PREFETCH" 320(%0)\n"
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#endif
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"movq 32(%0), %%mm4\n"
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"movq 40(%0), %%mm5\n"
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"movq 48(%0), %%mm6\n"
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"movq 56(%0), %%mm7\n"
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MOVNTQ" %%mm0, (%1)\n"
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MOVNTQ" %%mm1, 8(%1)\n"
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MOVNTQ" %%mm2, 16(%1)\n"
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MOVNTQ" %%mm3, 24(%1)\n"
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MOVNTQ" %%mm4, 32(%1)\n"
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MOVNTQ" %%mm5, 40(%1)\n"
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MOVNTQ" %%mm6, 48(%1)\n"
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MOVNTQ" %%mm7, 56(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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((const unsigned char *)from)+=64;
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((unsigned char *)to)+=64;
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}
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#endif /* Have SSE */
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#ifdef HAVE_MMX2
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/* since movntq is weakly-ordered, a "sfence"
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* is needed to become ordered again. */
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__asm__ __volatile__ ("sfence":::"memory");
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#endif
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#ifndef HAVE_SSE
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/* enables to use FPU */
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__asm__ __volatile__ (EMMS:::"memory");
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#endif
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}
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/*
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* Now do the tail of the block
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*/
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if(len) small_memcpy(to, from, len);
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return retval;
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}
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/**
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* special copy routine for mem -> agp/pci copy (based upon fast_memcpy)
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*/
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static void * RENAME(mem2agpcpy)(void * to, const void * from, size_t len)
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{
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void *retval;
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size_t i;
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retval = to;
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#ifdef STATISTICS
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{
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static int freq[33];
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static int t=0;
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int i;
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for(i=0; len>(1<<i); i++);
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freq[i]++;
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t++;
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if(1024*1024*1024 % t == 0)
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for(i=0; i<32; i++)
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printf("mem2agp freq < %8d %4d\n", 1<<i, freq[i]);
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}
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#endif
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if(len >= MIN_LEN)
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{
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register unsigned long int delta;
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/* Align destinition to MMREG_SIZE -boundary */
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delta = ((unsigned long int)to)&7;
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if(delta)
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{
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delta=8-delta;
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len -= delta;
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small_memcpy(to, from, delta);
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}
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i = len >> 6; /* len/64 */
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len &= 63;
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/*
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This algorithm is top effective when the code consequently
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|
reads and writes blocks which have size of cache line.
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|
Size of cache line is processor-dependent.
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|
It will, however, be a minimum of 32 bytes on any processors.
|
|
It would be better to have a number of instructions which
|
|
perform reading and writing to be multiple to a number of
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processor's decoders, but it's not always possible.
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*/
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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PREFETCH" 320(%0)\n"
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"movq 32(%0), %%mm4\n"
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"movq 40(%0), %%mm5\n"
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"movq 48(%0), %%mm6\n"
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"movq 56(%0), %%mm7\n"
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MOVNTQ" %%mm0, (%1)\n"
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MOVNTQ" %%mm1, 8(%1)\n"
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MOVNTQ" %%mm2, 16(%1)\n"
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MOVNTQ" %%mm3, 24(%1)\n"
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MOVNTQ" %%mm4, 32(%1)\n"
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MOVNTQ" %%mm5, 40(%1)\n"
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MOVNTQ" %%mm6, 48(%1)\n"
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MOVNTQ" %%mm7, 56(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from=((const unsigned char *)from)+64;
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to=((unsigned char *)to)+64;
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}
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#ifdef HAVE_MMX2
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/* since movntq is weakly-ordered, a "sfence"
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* is needed to become ordered again. */
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__asm__ __volatile__ ("sfence":::"memory");
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#endif
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/* enables to use FPU */
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__asm__ __volatile__ (EMMS:::"memory");
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}
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/*
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* Now do the tail of the block
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*/
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if(len) small_memcpy(to, from, len);
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return retval;
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}
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