mirror of https://github.com/mpv-player/mpv
1529 lines
44 KiB
C
1529 lines
44 KiB
C
/*
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Matrox MGA driver
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ported to VIDIX by Alex Beregszaszi
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YUY2 support (see config.format) added by A'rpi/ESP-team
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double buffering added by A'rpi/ESP-team
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Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me
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TODO:
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* fix memory size detection (current reading pci userconfig isn't
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working as requested - returns the max avail. ram on arch?)
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* translate all non-english comments to english
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*/
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/*
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* Original copyright:
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*
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* mga_vid.c
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*
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* Copyright (C) 1999 Aaron Holtzman
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*
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* Module skeleton based on gutted agpgart module by Jeff Hartmann
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* <slicer@ionet.net>
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*
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* Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0
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*
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* BES == Back End Scaler
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*
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* This software has been released under the terms of the GNU Public
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* license. See http://www.gnu.org/copyleft/gpl.html for details.
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*/
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//#define CRTC2
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// Set this value, if autodetection fails! (video ram size in megabytes)
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//#define MGA_MEMORY_SIZE 16
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/* No irq support in userspace implemented yet, do not enable this! */
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/* disable irq */
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#undef MGA_ALLOW_IRQ
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#define MGA_VSYNC_POS 2
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#undef MGA_PCICONFIG_MEMDETECT
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#define MGA_DEFAULT_FRAMES 4
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#include <errno.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <math.h>
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#include <inttypes.h>
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#include "vidix.h"
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#include "vidixlib.h"
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#include "fourcc.h"
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#include "../libdha/libdha.h"
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#include "../libdha/pci_ids.h"
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#include "../libdha/pci_names.h"
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#ifdef __MINGW32__
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#define ENOTSUP 134
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#endif
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#if !defined(ENOTSUP) && defined(EOPNOTSUPP)
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#define ENOTSUP EOPNOTSUPP
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#endif
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/* from radeon_vid */
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#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ))))
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#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL
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#define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0)
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#define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val)
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#define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0)
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#define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val)
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static int mga_verbose = 0;
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/* for device detection */
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static int probed = 0;
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static pciinfo_t pci_info;
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/* internal booleans */
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static int mga_vid_in_use = 0;
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static int is_g400 = 0;
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static int vid_src_ready = 0;
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static int vid_overlay_on = 0;
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/* mapped physical addresses */
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static uint8_t *mga_mmio_base = 0;
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static uint8_t *mga_mem_base = 0;
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static int mga_src_base = 0; /* YUV buffer position in video memory */
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static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */
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/* Graphic keys */
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static vidix_grkey_t mga_grkey;
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static int colkey_saved = 0;
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static int colkey_on = 0;
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static unsigned char colkey_color[4];
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static unsigned char colkey_mask[4];
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/* for IRQ */
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static int mga_irq = -1;
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static int mga_next_frame = 0;
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static vidix_capability_t mga_cap =
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{
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"Matrox MGA G200/G4x0/G5x0 YUV Video",
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"Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev",
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TYPE_OUTPUT,
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{ 0, 0, 0, 0 },
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2048,
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2048,
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4,
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4,
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-1,
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FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
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VENDOR_MATROX,
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-1, /* will be set in vixProbe */
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{ 0, 0, 0, 0}
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};
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/* MATROX BES registers */
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typedef struct bes_registers_s
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{
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//BES Control
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uint32_t besctl;
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//BES Global control
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uint32_t besglobctl;
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//Luma control (brightness and contrast)
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uint32_t beslumactl;
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//Line pitch
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uint32_t bespitch;
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//Buffer A-1 Chroma 3 plane org
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uint32_t besa1c3org;
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//Buffer A-1 Chroma org
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uint32_t besa1corg;
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//Buffer A-1 Luma org
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uint32_t besa1org;
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//Buffer A-2 Chroma 3 plane org
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uint32_t besa2c3org;
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//Buffer A-2 Chroma org
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uint32_t besa2corg;
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//Buffer A-2 Luma org
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uint32_t besa2org;
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//Buffer B-1 Chroma 3 plane org
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uint32_t besb1c3org;
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//Buffer B-1 Chroma org
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uint32_t besb1corg;
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//Buffer B-1 Luma org
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uint32_t besb1org;
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//Buffer B-2 Chroma 3 plane org
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uint32_t besb2c3org;
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//Buffer B-2 Chroma org
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uint32_t besb2corg;
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//Buffer B-2 Luma org
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uint32_t besb2org;
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//BES Horizontal coord
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uint32_t beshcoord;
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//BES Horizontal inverse scaling [5.14]
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uint32_t beshiscal;
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//BES Horizontal source start [10.14] (for scaling)
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uint32_t beshsrcst;
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//BES Horizontal source ending [10.14] (for scaling)
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uint32_t beshsrcend;
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//BES Horizontal source last
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uint32_t beshsrclst;
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//BES Vertical coord
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uint32_t besvcoord;
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//BES Vertical inverse scaling [5.14]
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uint32_t besviscal;
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//BES Field 1 vertical source last position
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uint32_t besv1srclst;
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//BES Field 1 weight start
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uint32_t besv1wght;
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//BES Field 2 vertical source last position
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uint32_t besv2srclst;
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//BES Field 2 weight start
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uint32_t besv2wght;
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} bes_registers_t;
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static bes_registers_t regs;
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#ifdef CRTC2
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typedef struct crtc2_registers_s
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{
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uint32_t c2ctl;
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uint32_t c2datactl;
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uint32_t c2misc;
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uint32_t c2hparam;
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uint32_t c2hsync;
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uint32_t c2offset;
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uint32_t c2pl2startadd0;
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uint32_t c2pl2startadd1;
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uint32_t c2pl3startadd0;
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uint32_t c2pl3startadd1;
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uint32_t c2preload;
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uint32_t c2spicstartadd0;
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uint32_t c2spicstartadd1;
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uint32_t c2startadd0;
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uint32_t c2startadd1;
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uint32_t c2subpiclut;
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uint32_t c2vcount;
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uint32_t c2vparam;
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uint32_t c2vsync;
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} crtc2_registers_t;
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static crtc2_registers_t cregs;
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#endif
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//All register offsets are converted to word aligned offsets (32 bit)
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//because we want all our register accesses to be 32 bits
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#define VCOUNT 0x1e20
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#define PALWTADD 0x3c00 // Index register for X_DATAREG port
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#define X_DATAREG 0x3c0a
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#define XMULCTRL 0x19
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#define BPP_8 0x00
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#define BPP_15 0x01
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#define BPP_16 0x02
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#define BPP_24 0x03
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#define BPP_32_DIR 0x04
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#define BPP_32_PAL 0x07
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#define XCOLMSK 0x40
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#define X_COLKEY 0x42
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#define XKEYOPMODE 0x51
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#define XCOLMSK0RED 0x52
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#define XCOLMSK0GREEN 0x53
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#define XCOLMSK0BLUE 0x54
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#define XCOLKEY0RED 0x55
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#define XCOLKEY0GREEN 0x56
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#define XCOLKEY0BLUE 0x57
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#ifdef CRTC2
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/*CRTC2 registers*/
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#define XMISCCTRL 0x1e
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#define C2CTL 0x3c10
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#define C2DATACTL 0x3c4c
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#define C2MISC 0x3c44
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#define C2HPARAM 0x3c14
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#define C2HSYNC 0x3c18
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#define C2OFFSET 0x3c40
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#define C2PL2STARTADD0 0x3c30 // like BESA1CORG
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#define C2PL2STARTADD1 0x3c34 // like BESA2CORG
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#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG
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#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG
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#define C2PRELOAD 0x3c24
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#define C2SPICSTARTADD0 0x3c54
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#define C2SPICSTARTADD1 0x3c58
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#define C2STARTADD0 0x3c28 // like BESA1ORG
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#define C2STARTADD1 0x3c2c // like BESA2ORG
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#define C2SUBPICLUT 0x3c50
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#define C2VCOUNT 0x3c48
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#define C2VPARAM 0x3c1c
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#define C2VSYNC 0x3c20
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#endif /* CRTC2 */
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// Backend Scaler registers
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#define BESCTL 0x3d20
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#define BESGLOBCTL 0x3dc0
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#define BESLUMACTL 0x3d40
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#define BESPITCH 0x3d24
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#define BESA1C3ORG 0x3d60
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#define BESA1CORG 0x3d10
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#define BESA1ORG 0x3d00
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#define BESA2C3ORG 0x3d64
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#define BESA2CORG 0x3d14
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#define BESA2ORG 0x3d04
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#define BESB1C3ORG 0x3d68
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#define BESB1CORG 0x3d18
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#define BESB1ORG 0x3d08
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#define BESB2C3ORG 0x3d6C
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#define BESB2CORG 0x3d1C
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#define BESB2ORG 0x3d0C
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#define BESHCOORD 0x3d28
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#define BESHISCAL 0x3d30
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#define BESHSRCEND 0x3d3C
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#define BESHSRCLST 0x3d50
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#define BESHSRCST 0x3d38
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#define BESV1WGHT 0x3d48
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#define BESV2WGHT 0x3d4c
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#define BESV1SRCLST 0x3d54
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#define BESV2SRCLST 0x3d58
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#define BESVISCAL 0x3d34
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#define BESVCOORD 0x3d2c
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#define BESSTATUS 0x3dc4
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#define CRTCX 0x1fd4
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#define CRTCD 0x1fd5
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#define IEN 0x1e1c
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#define ICLEAR 0x1e18
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#define STATUS 0x1e14
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#ifdef CRTC2
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static void crtc2_frame_sel(int frame)
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{
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switch(frame) {
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case 0:
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cregs.c2pl2startadd0=regs.besa1corg;
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cregs.c2pl3startadd0=regs.besa1c3org;
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cregs.c2startadd0=regs.besa1org;
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break;
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case 1:
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cregs.c2pl2startadd0=regs.besa2corg;
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cregs.c2pl3startadd0=regs.besa2c3org;
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cregs.c2startadd0=regs.besa2org;
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break;
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case 2:
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cregs.c2pl2startadd0=regs.besb1corg;
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cregs.c2pl3startadd0=regs.besb1c3org;
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cregs.c2startadd0=regs.besb1org;
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break;
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case 3:
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cregs.c2pl2startadd0=regs.besb2corg;
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cregs.c2pl3startadd0=regs.besb2c3org;
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cregs.c2startadd0=regs.besb2org;
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break;
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}
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writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
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writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
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writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
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}
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#endif
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static int mga_frame_select(unsigned int frame)
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{
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mga_next_frame = frame;
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if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame);
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#if MGA_ALLOW_IRQ
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if (mga_irq == -1)
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#endif
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{
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//we don't need the vcount protection as we're only hitting
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//one register (and it doesn't seem to be double buffered)
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regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
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writel( regs.besctl, mga_mmio_base + BESCTL );
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// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
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writel( regs.besglobctl + (MGA_VSYNC_POS<<16),
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mga_mmio_base + BESGLOBCTL);
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#ifdef CRTC2
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crtc2_frame_sel(mga_next_frame);
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#endif
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}
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return(0);
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}
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static void mga_vid_write_regs(int restore)
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{
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//Make sure internal registers don't get updated until we're done
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writel( (readl(mga_mmio_base + VCOUNT)-1)<<16,
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mga_mmio_base + BESGLOBCTL);
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// color or coordinate keying
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if(restore && colkey_saved){
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// restore it
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colkey_saved=0;
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// printf("[mga] Restoring colorkey (ON: %d %02X:%02X:%02X)\n",
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// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]);
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// Set color key registers:
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writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
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writeb( colkey_on, mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
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writeb( colkey_color[0], mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
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writeb( colkey_color[1], mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
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writeb( colkey_color[2], mga_mmio_base + X_DATAREG);
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writeb( X_COLKEY, mga_mmio_base + PALWTADD);
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writeb( colkey_color[3], mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
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writeb( colkey_mask[0], mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
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writeb( colkey_mask[1], mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
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writeb( colkey_mask[2], mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK, mga_mmio_base + PALWTADD);
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writeb( colkey_mask[3], mga_mmio_base + X_DATAREG);
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} else if(!colkey_saved){
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// save it
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colkey_saved=1;
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// Get color key registers:
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writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
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colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1;
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writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
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colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
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colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
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colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( X_COLKEY, mga_mmio_base + PALWTADD);
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colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
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colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
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colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
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colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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writeb( XCOLMSK, mga_mmio_base + PALWTADD);
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colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG);
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// printf("[mga] Saved colorkey (ON: %d %02X:%02X:%02X)\n",
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// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]);
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}
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if(!restore){
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writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
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writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG);
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if ( mga_grkey.ckey.op == CKEY_TRUE )
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{
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uint32_t r=0, g=0, b=0;
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writeb( XMULCTRL, mga_mmio_base + PALWTADD);
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switch (readb (mga_mmio_base + X_DATAREG))
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{
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case BPP_8:
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/* Need to look up the color index, just using
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color 0 for now. */
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break;
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case BPP_15:
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r = mga_grkey.ckey.red >> 3;
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g = mga_grkey.ckey.green >> 3;
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b = mga_grkey.ckey.blue >> 3;
|
|
break;
|
|
|
|
case BPP_16:
|
|
r = mga_grkey.ckey.red >> 3;
|
|
g = mga_grkey.ckey.green >> 2;
|
|
b = mga_grkey.ckey.blue >> 3;
|
|
break;
|
|
|
|
case BPP_24:
|
|
case BPP_32_DIR:
|
|
case BPP_32_PAL:
|
|
r = mga_grkey.ckey.red;
|
|
g = mga_grkey.ckey.green;
|
|
b = mga_grkey.ckey.blue;
|
|
break;
|
|
}
|
|
|
|
// Enable colorkeying
|
|
writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
|
|
writeb( 1, mga_mmio_base + X_DATAREG);
|
|
|
|
// Disable color keying on alpha channel
|
|
writeb( XCOLMSK, mga_mmio_base + PALWTADD);
|
|
writeb( 0x00, mga_mmio_base + X_DATAREG);
|
|
writeb( X_COLKEY, mga_mmio_base + PALWTADD);
|
|
writeb( 0x00, mga_mmio_base + X_DATAREG);
|
|
|
|
|
|
// Set up color key registers
|
|
writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD);
|
|
writeb( r, mga_mmio_base + X_DATAREG);
|
|
writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD);
|
|
writeb( g, mga_mmio_base + X_DATAREG);
|
|
writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD);
|
|
writeb( b, mga_mmio_base + X_DATAREG);
|
|
|
|
// Set up color key mask registers
|
|
writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD);
|
|
writeb( 0xff, mga_mmio_base + X_DATAREG);
|
|
writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD);
|
|
writeb( 0xff, mga_mmio_base + X_DATAREG);
|
|
writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD);
|
|
writeb( 0xff, mga_mmio_base + X_DATAREG);
|
|
}
|
|
else
|
|
{
|
|
// Disable colorkeying
|
|
writeb( XKEYOPMODE, mga_mmio_base + PALWTADD);
|
|
writeb( 0, mga_mmio_base + X_DATAREG);
|
|
}
|
|
}
|
|
|
|
// Backend Scaler
|
|
writel( regs.besctl, mga_mmio_base + BESCTL);
|
|
if(is_g400)
|
|
writel( regs.beslumactl, mga_mmio_base + BESLUMACTL);
|
|
writel( regs.bespitch, mga_mmio_base + BESPITCH);
|
|
|
|
writel( regs.besa1org, mga_mmio_base + BESA1ORG);
|
|
writel( regs.besa1corg, mga_mmio_base + BESA1CORG);
|
|
writel( regs.besa2org, mga_mmio_base + BESA2ORG);
|
|
writel( regs.besa2corg, mga_mmio_base + BESA2CORG);
|
|
writel( regs.besb1org, mga_mmio_base + BESB1ORG);
|
|
writel( regs.besb1corg, mga_mmio_base + BESB1CORG);
|
|
writel( regs.besb2org, mga_mmio_base + BESB2ORG);
|
|
writel( regs.besb2corg, mga_mmio_base + BESB2CORG);
|
|
if(is_g400)
|
|
{
|
|
writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG);
|
|
writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG);
|
|
writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG);
|
|
writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG);
|
|
}
|
|
|
|
writel( regs.beshcoord, mga_mmio_base + BESHCOORD);
|
|
writel( regs.beshiscal, mga_mmio_base + BESHISCAL);
|
|
writel( regs.beshsrcst, mga_mmio_base + BESHSRCST);
|
|
writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND);
|
|
writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST);
|
|
|
|
writel( regs.besvcoord, mga_mmio_base + BESVCOORD);
|
|
writel( regs.besviscal, mga_mmio_base + BESVISCAL);
|
|
|
|
writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST);
|
|
writel( regs.besv1wght, mga_mmio_base + BESV1WGHT);
|
|
writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST);
|
|
writel( regs.besv2wght, mga_mmio_base + BESV2WGHT);
|
|
|
|
//update the registers somewhere between 1 and 2 frames from now.
|
|
writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16),
|
|
mga_mmio_base + BESGLOBCTL);
|
|
|
|
if (mga_verbose > 1)
|
|
{
|
|
printf("[mga] wrote BES registers\n");
|
|
printf("[mga] BESCTL = 0x%08x\n",
|
|
readl(mga_mmio_base + BESCTL));
|
|
printf("[mga] BESGLOBCTL = 0x%08x\n",
|
|
readl(mga_mmio_base + BESGLOBCTL));
|
|
printf("[mga] BESSTATUS= 0x%08x\n",
|
|
readl(mga_mmio_base + BESSTATUS));
|
|
}
|
|
#ifdef CRTC2
|
|
// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
|
|
// printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC));
|
|
// printf("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl);
|
|
|
|
// writel(cregs.c2ctl, mga_mmio_base + C2CTL);
|
|
|
|
writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL);
|
|
writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL);
|
|
// ctrc2
|
|
// disable CRTC2 acording to specs
|
|
// writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL);
|
|
// je to treba ???
|
|
// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel
|
|
// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL);
|
|
// writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL);
|
|
// writel(cregs.c2datactl, mga_mmio_base + C2DATACTL);
|
|
// writel(cregs.c2hparam, mga_mmio_base + C2HPARAM);
|
|
// writel(cregs.c2hsync, mga_mmio_base + C2HSYNC);
|
|
// writel(cregs.c2vparam, mga_mmio_base + C2VPARAM);
|
|
// writel(cregs.c2vsync, mga_mmio_base + C2VSYNC);
|
|
writel(cregs.c2misc, mga_mmio_base + C2MISC);
|
|
|
|
if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset);
|
|
|
|
writel(cregs.c2offset, mga_mmio_base + C2OFFSET);
|
|
writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0);
|
|
// writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1);
|
|
writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0);
|
|
// writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1);
|
|
writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0);
|
|
// writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1);
|
|
writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0);
|
|
// writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1);
|
|
// writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT);
|
|
// writel(cregs.c2preload, mga_mmio_base + C2PRELOAD);
|
|
// finaly enable everything
|
|
// writel(cregs.c2ctl, mga_mmio_base + C2CTL);
|
|
// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL));
|
|
// printf("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC));
|
|
#endif
|
|
}
|
|
|
|
#ifdef MGA_ALLOW_IRQ
|
|
static void enable_irq(){
|
|
long int cc;
|
|
|
|
cc = readl(mga_mmio_base + IEN);
|
|
// printf("*** !!! IRQREG = %d\n", (int)(cc&0xff));
|
|
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
|
|
writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */
|
|
writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */
|
|
|
|
writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL);
|
|
|
|
return;
|
|
}
|
|
|
|
static void disable_irq()
|
|
{
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */
|
|
|
|
return;
|
|
}
|
|
|
|
void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) {
|
|
// static int frame=0;
|
|
// static int counter=0;
|
|
long int cc;
|
|
// if ( ! mga_enabled_flag ) return;
|
|
|
|
// printf("vcount = %d\n",readl(mga_mmio_base + VCOUNT));
|
|
|
|
//printf("mga_interrupt #%d\n", irq);
|
|
|
|
if ( irq != -1 ) {
|
|
|
|
cc = readl(mga_mmio_base + STATUS);
|
|
if ( ! (cc & 0x10) ) return; /* vsyncpen */
|
|
// debug_irqcnt++;
|
|
}
|
|
|
|
// if ( debug_irqignore ) {
|
|
// debug_irqignore = 0;
|
|
|
|
|
|
/*
|
|
if ( mga_conf_deinterlace ) {
|
|
if ( mga_first_field ) {
|
|
// printf("mga_interrupt first field\n");
|
|
if ( syncfb_interrupt() )
|
|
mga_first_field = 0;
|
|
} else {
|
|
// printf("mga_interrupt second field\n");
|
|
mga_select_buffer( mga_current_field | 2 );
|
|
mga_first_field = 1;
|
|
}
|
|
} else {
|
|
syncfb_interrupt();
|
|
}
|
|
*/
|
|
|
|
// frame=(frame+1)&1;
|
|
regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25);
|
|
writel( regs.besctl, mga_mmio_base + BESCTL );
|
|
|
|
#ifdef CRTC2
|
|
// sem pridat vyber obrazku !!!!
|
|
crtc2_frame_sel(mga_next_frame);
|
|
#endif
|
|
|
|
#if 0
|
|
++counter;
|
|
if(!(counter&63)){
|
|
printf("mga irq counter = %d\n",counter);
|
|
}
|
|
#endif
|
|
|
|
// } else {
|
|
// debug_irqignore = 1;
|
|
// }
|
|
|
|
if ( irq != -1 ) {
|
|
writeb( 0x11, mga_mmio_base + CRTCX);
|
|
writeb( 0, mga_mmio_base + CRTCD );
|
|
writeb( 0x10, mga_mmio_base + CRTCD );
|
|
}
|
|
|
|
// writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL);
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
#endif /* MGA_ALLOW_IRQ */
|
|
|
|
static int mga_config_playback(vidix_playback_t *config)
|
|
{
|
|
unsigned int i;
|
|
int x, y, sw, sh, dw, dh;
|
|
int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights;
|
|
#ifdef CRTC2
|
|
#define right_margin 0
|
|
#define left_margin 18
|
|
#define hsync_len 46
|
|
#define lower_margin 10
|
|
#define vsync_len 4
|
|
#define upper_margin 39
|
|
|
|
unsigned int hdispend = (config->src.w + 31) & ~31;
|
|
unsigned int hsyncstart = hdispend + (right_margin & ~7);
|
|
unsigned int hsyncend = hsyncstart + (hsync_len & ~7);
|
|
unsigned int htotal = hsyncend + (left_margin & ~7);
|
|
unsigned int vdispend = config->src.h;
|
|
unsigned int vsyncstart = vdispend + lower_margin;
|
|
unsigned int vsyncend = vsyncstart + vsync_len;
|
|
unsigned int vtotal = vsyncend + upper_margin;
|
|
#endif
|
|
|
|
if ((config->num_frames < 1) || (config->num_frames > 4))
|
|
{
|
|
printf("[mga] illegal num_frames: %d, setting to %d\n",
|
|
config->num_frames, MGA_DEFAULT_FRAMES);
|
|
config->num_frames = MGA_DEFAULT_FRAMES;
|
|
}
|
|
|
|
x = config->dest.x;
|
|
y = config->dest.y;
|
|
sw = config->src.w;
|
|
sh = config->src.h;
|
|
dw = config->dest.w;
|
|
dh = config->dest.h;
|
|
|
|
config->dest.pitch.y=32;
|
|
config->dest.pitch.u=config->dest.pitch.v=32;
|
|
|
|
if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n",
|
|
dw, dh, x, y, sw, sh, config->fourcc);
|
|
|
|
if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4))
|
|
{
|
|
printf("[mga] Invalid src/dest dimensions\n");
|
|
return(EINVAL);
|
|
}
|
|
|
|
//FIXME check that window is valid and inside desktop
|
|
|
|
// printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT));
|
|
|
|
sw+=sw&1;
|
|
switch(config->fourcc)
|
|
{
|
|
case IMGFMT_I420:
|
|
case IMGFMT_IYUV:
|
|
case IMGFMT_YV12:
|
|
sh+=sh&1;
|
|
config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
|
|
break;
|
|
case IMGFMT_YUY2:
|
|
case IMGFMT_UYVY:
|
|
config->frame_size = ((sw + 31) & ~31) * sh * 2;
|
|
break;
|
|
default:
|
|
printf("[mga] Unsupported pixel format: %x\n", config->fourcc);
|
|
return(ENOTSUP);
|
|
}
|
|
|
|
config->offsets[0] = 0;
|
|
// config->offsets[1] = config->frame_size;
|
|
// config->offsets[2] = 2*config->frame_size;
|
|
// config->offsets[3] = 3*config->frame_size;
|
|
for (i = 1; i < config->num_frames+1; i++)
|
|
config->offsets[i] = i*config->frame_size;
|
|
|
|
config->offset.y=0;
|
|
if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV)
|
|
{
|
|
config->offset.u=((sw + 31) & ~31) * sh;
|
|
config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4;
|
|
}
|
|
else {
|
|
config->offset.v=((sw + 31) & ~31) * sh;
|
|
config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4;
|
|
}
|
|
|
|
//FIXME figure out a better way to allocate memory on card
|
|
//allocate 2 megs
|
|
//mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000;
|
|
//mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000;
|
|
|
|
mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size);
|
|
if (mga_src_base < 0)
|
|
{
|
|
printf("[mga] not enough memory for frames!\n");
|
|
return(EFAULT);
|
|
}
|
|
mga_src_base &= (~0xFFFF); /* 64k boundary */
|
|
if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base);
|
|
|
|
config->dga_addr = mga_mem_base + mga_src_base;
|
|
|
|
/* for G200 set Interleaved UV planes */
|
|
if (!is_g400)
|
|
config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV;
|
|
|
|
//Setup the BES registers for a three plane 4:2:0 video source
|
|
|
|
regs.besglobctl = 0;
|
|
|
|
switch(config->fourcc)
|
|
{
|
|
case IMGFMT_YV12:
|
|
case IMGFMT_I420:
|
|
case IMGFMT_IYUV:
|
|
regs.besctl = 1 // BES enabled
|
|
+ (0<<6) // even start polarity
|
|
+ (1<<10) // x filtering enabled
|
|
+ (1<<11) // y filtering enabled
|
|
+ (1<<16) // chroma upsampling
|
|
+ (1<<17) // 4:2:0 mode
|
|
+ (1<<18); // dither enabled
|
|
#if 0
|
|
if(is_g400)
|
|
{
|
|
//zoom disabled, zoom filter disabled, 420 3 plane format, proc amp
|
|
//disabled, rgb mode disabled
|
|
regs.besglobctl = (1<<5);
|
|
}
|
|
else
|
|
{
|
|
//zoom disabled, zoom filter disabled, Cb samples in 0246, Cr
|
|
//in 1357, BES register update on besvcnt
|
|
regs.besglobctl = 0;
|
|
}
|
|
#endif
|
|
break;
|
|
|
|
case IMGFMT_YUY2:
|
|
regs.besctl = 1 // BES enabled
|
|
+ (0<<6) // even start polarity
|
|
+ (1<<10) // x filtering enabled
|
|
+ (1<<11) // y filtering enabled
|
|
+ (1<<16) // chroma upsampling
|
|
+ (0<<17) // 4:2:2 mode
|
|
+ (1<<18); // dither enabled
|
|
|
|
regs.besglobctl = 0; // YUY2 format selected
|
|
break;
|
|
|
|
case IMGFMT_UYVY:
|
|
regs.besctl = 1 // BES enabled
|
|
+ (0<<6) // even start polarity
|
|
+ (1<<10) // x filtering enabled
|
|
+ (1<<11) // y filtering enabled
|
|
+ (1<<16) // chroma upsampling
|
|
+ (0<<17) // 4:2:2 mode
|
|
+ (1<<18); // dither enabled
|
|
|
|
regs.besglobctl = 1<<6; // UYVY format selected
|
|
break;
|
|
|
|
}
|
|
|
|
//Disable contrast and brightness control
|
|
regs.besglobctl |= (1<<5) + (1<<7);
|
|
regs.beslumactl = (0x7f << 16) + (0x80<<0);
|
|
regs.beslumactl = 0x80<<0;
|
|
|
|
//Setup destination window boundaries
|
|
besleft = x > 0 ? x : 0;
|
|
bestop = y > 0 ? y : 0;
|
|
regs.beshcoord = (besleft<<16) + (x + dw-1);
|
|
regs.besvcoord = (bestop<<16) + (y + dh-1);
|
|
|
|
//Setup source dimensions
|
|
regs.beshsrclst = (sw - 1) << 16;
|
|
regs.bespitch = (sw + 31) & ~31 ;
|
|
|
|
//Setup horizontal scaling
|
|
ifactor = ((sw-1)<<14)/(dw-1);
|
|
ofsleft = besleft - x;
|
|
|
|
regs.beshiscal = ifactor<<2;
|
|
regs.beshsrcst = (ofsleft*ifactor)<<2;
|
|
regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2);
|
|
|
|
//Setup vertical scaling
|
|
ifactor = ((sh-1)<<14)/(dh-1);
|
|
ofstop = bestop - y;
|
|
|
|
regs.besviscal = ifactor<<2;
|
|
|
|
baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch;
|
|
//frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2;
|
|
regs.besa1org = (uint32_t) mga_src_base + baseadrofs;
|
|
regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size;
|
|
regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size;
|
|
regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size;
|
|
|
|
if(config->fourcc==IMGFMT_YV12
|
|
||config->fourcc==IMGFMT_IYUV
|
|
||config->fourcc==IMGFMT_I420
|
|
){
|
|
// planar YUV frames:
|
|
if (is_g400)
|
|
baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch;
|
|
else
|
|
baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch;
|
|
|
|
if(config->fourcc==IMGFMT_YV12){
|
|
regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
|
|
regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
|
|
regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
|
|
regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
|
|
regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4);
|
|
regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4);
|
|
regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4);
|
|
regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4);
|
|
} else {
|
|
regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ;
|
|
regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh;
|
|
regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh;
|
|
regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh;
|
|
regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4);
|
|
regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4);
|
|
regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4);
|
|
regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4);
|
|
}
|
|
|
|
}
|
|
|
|
weight = ofstop * (regs.besviscal >> 2);
|
|
weights = weight < 0 ? 1 : 0;
|
|
regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2);
|
|
regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF);
|
|
|
|
#ifdef CRTC2
|
|
// pridat hlavni registry - tj. casovani ...
|
|
|
|
|
|
switch(config->fourcc){
|
|
case IMGFMT_YV12:
|
|
case IMGFMT_I420:
|
|
case IMGFMT_IYUV:
|
|
cregs.c2ctl = 1 // CRTC2 enabled
|
|
+ (1<<1) // external clock
|
|
+ (0<<2) // external clock
|
|
+ (1<<3) // pixel clock enable - not needed ???
|
|
+ (0<<4) // high prioryty req
|
|
+ (1<<5) // high prioryty req
|
|
+ (0<<6) // high prioryty req
|
|
+ (1<<8) // high prioryty req max
|
|
+ (0<<9) // high prioryty req max
|
|
+ (0<<10) // high prioryty req max
|
|
+ (0<<20) // CRTC1 to DAC
|
|
+ (1<<21) // 420 mode
|
|
+ (1<<22) // 420 mode
|
|
+ (1<<23) // 420 mode
|
|
+ (0<<24) // single chroma line for 420 mode - need to be corrected
|
|
+ (0<<25) /*/ interlace mode - need to be corrected*/
|
|
+ (0<<26) // field legth polariry
|
|
+ (0<<27) // field identification polariry
|
|
+ (1<<28) // VIDRST detection mode
|
|
+ (0<<29) // VIDRST detection mode
|
|
+ (1<<30) // Horizontal counter preload
|
|
+ (1<<31) // Vertical counter preload
|
|
;
|
|
cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
|
|
+ (1<<1) // Y filter enable
|
|
+ (1<<2) // CbCr filter enable
|
|
+ (0<<3) // subpicture enable (disabled)
|
|
+ (0<<4) // NTSC enable (disabled - PAL)
|
|
+ (0<<5) // C2 static subpicture enable (disabled)
|
|
+ (0<<6) // C2 subpicture offset division (disabled)
|
|
+ (0<<7) // 422 subformat selection !
|
|
/* + (0<<8) // 15 bpp high alpha
|
|
+ (0<<9) // 15 bpp high alpha
|
|
+ (0<<10) // 15 bpp high alpha
|
|
+ (0<<11) // 15 bpp high alpha
|
|
+ (0<<12) // 15 bpp high alpha
|
|
+ (0<<13) // 15 bpp high alpha
|
|
+ (0<<14) // 15 bpp high alpha
|
|
+ (0<<15) // 15 bpp high alpha
|
|
+ (0<<16) // 15 bpp low alpha
|
|
+ (0<<17) // 15 bpp low alpha
|
|
+ (0<<18) // 15 bpp low alpha
|
|
+ (0<<19) // 15 bpp low alpha
|
|
+ (0<<20) // 15 bpp low alpha
|
|
+ (0<<21) // 15 bpp low alpha
|
|
+ (0<<22) // 15 bpp low alpha
|
|
+ (0<<23) // 15 bpp low alpha
|
|
+ (0<<24) // static subpicture key
|
|
+ (0<<25) // static subpicture key
|
|
+ (0<<26) // static subpicture key
|
|
+ (0<<27) // static subpicture key
|
|
+ (0<<28) // static subpicture key
|
|
*/ ;
|
|
break;
|
|
|
|
case IMGFMT_YUY2:
|
|
cregs.c2ctl = 1 // CRTC2 enabled
|
|
+ (1<<1) // external clock
|
|
+ (0<<2) // external clock
|
|
+ (1<<3) // pixel clock enable - not needed ???
|
|
+ (0<<4) // high prioryty req - acc to spec
|
|
+ (1<<5) // high prioryty req
|
|
+ (0<<6) // high prioryty req
|
|
// 7 reserved
|
|
+ (1<<8) // high prioryty req max
|
|
+ (0<<9) // high prioryty req max
|
|
+ (0<<10) // high prioryty req max
|
|
// 11-19 reserved
|
|
+ (0<<20) // CRTC1 to DAC
|
|
+ (1<<21) // 422 mode
|
|
+ (0<<22) // 422 mode
|
|
+ (1<<23) // 422 mode
|
|
+ (0<<24) // single chroma line for 420 mode - need to be corrected
|
|
+ (0<<25) /*/ interlace mode - need to be corrected*/
|
|
+ (0<<26) // field legth polariry
|
|
+ (0<<27) // field identification polariry
|
|
+ (1<<28) // VIDRST detection mode
|
|
+ (0<<29) // VIDRST detection mode
|
|
+ (1<<30) // Horizontal counter preload
|
|
+ (1<<31) // Vertical counter preload
|
|
;
|
|
cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode
|
|
+ (1<<1) // Y filter enable
|
|
+ (1<<2) // CbCr filter enable
|
|
+ (0<<3) // subpicture enable (disabled)
|
|
+ (0<<4) // NTSC enable (disabled - PAL)
|
|
+ (0<<5) // C2 static subpicture enable (disabled)
|
|
+ (0<<6) // C2 subpicture offset division (disabled)
|
|
+ (0<<7) // 422 subformat selection !
|
|
/* + (0<<8) // 15 bpp high alpha
|
|
+ (0<<9) // 15 bpp high alpha
|
|
+ (0<<10) // 15 bpp high alpha
|
|
+ (0<<11) // 15 bpp high alpha
|
|
+ (0<<12) // 15 bpp high alpha
|
|
+ (0<<13) // 15 bpp high alpha
|
|
+ (0<<14) // 15 bpp high alpha
|
|
+ (0<<15) // 15 bpp high alpha
|
|
+ (0<<16) // 15 bpp low alpha
|
|
+ (0<<17) // 15 bpp low alpha
|
|
+ (0<<18) // 15 bpp low alpha
|
|
+ (0<<19) // 15 bpp low alpha
|
|
+ (0<<20) // 15 bpp low alpha
|
|
+ (0<<21) // 15 bpp low alpha
|
|
+ (0<<22) // 15 bpp low alpha
|
|
+ (0<<23) // 15 bpp low alpha
|
|
+ (0<<24) // static subpicture key
|
|
+ (0<<25) // static subpicture key
|
|
+ (0<<26) // static subpicture key
|
|
+ (0<<27) // static subpicture key
|
|
+ (0<<28) // static subpicture key
|
|
*/ ;
|
|
break;
|
|
|
|
case IMGFMT_UYVY:
|
|
cregs.c2ctl = 1 // CRTC2 enabled
|
|
+ (1<<1) // external clock
|
|
+ (0<<2) // external clock
|
|
+ (1<<3) // pixel clock enable - not needed ???
|
|
+ (0<<4) // high prioryty req
|
|
+ (1<<5) // high prioryty req
|
|
+ (0<<6) // high prioryty req
|
|
+ (1<<8) // high prioryty req max
|
|
+ (0<<9) // high prioryty req max
|
|
+ (0<<10) // high prioryty req max
|
|
+ (0<<20) // CRTC1 to DAC
|
|
+ (1<<21) // 422 mode
|
|
+ (0<<22) // 422 mode
|
|
+ (1<<23) // 422 mode
|
|
+ (1<<24) // single chroma line for 420 mode - need to be corrected
|
|
+ (1<<25) /*/ interlace mode - need to be corrected*/
|
|
+ (0<<26) // field legth polariry
|
|
+ (0<<27) // field identification polariry
|
|
+ (1<<28) // VIDRST detection mode
|
|
+ (0<<29) // VIDRST detection mode
|
|
+ (1<<30) // Horizontal counter preload
|
|
+ (1<<31) // Vertical counter preload
|
|
;
|
|
cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode
|
|
+ (1<<1) // Y filter enable
|
|
+ (1<<2) // CbCr filter enable
|
|
+ (0<<3) // subpicture enable (disabled)
|
|
+ (0<<4) // NTSC enable (disabled - PAL)
|
|
+ (0<<5) // C2 static subpicture enable (disabled)
|
|
+ (0<<6) // C2 subpicture offset division (disabled)
|
|
+ (1<<7) // 422 subformat selection !
|
|
/* + (0<<8) // 15 bpp high alpha
|
|
+ (0<<9) // 15 bpp high alpha
|
|
+ (0<<10) // 15 bpp high alpha
|
|
+ (0<<11) // 15 bpp high alpha
|
|
+ (0<<12) // 15 bpp high alpha
|
|
+ (0<<13) // 15 bpp high alpha
|
|
+ (0<<14) // 15 bpp high alpha
|
|
+ (0<<15) // 15 bpp high alpha
|
|
+ (0<<16) // 15 bpp low alpha
|
|
+ (0<<17) // 15 bpp low alpha
|
|
+ (0<<18) // 15 bpp low alpha
|
|
+ (0<<19) // 15 bpp low alpha
|
|
+ (0<<20) // 15 bpp low alpha
|
|
+ (0<<21) // 15 bpp low alpha
|
|
+ (0<<22) // 15 bpp low alpha
|
|
+ (0<<23) // 15 bpp low alpha
|
|
+ (0<<24) // static subpicture key
|
|
+ (0<<25) // static subpicture key
|
|
+ (0<<26) // static subpicture key
|
|
+ (0<<27) // static subpicture key
|
|
+ (0<<28) // static subpicture key
|
|
*/ ;
|
|
break;
|
|
}
|
|
|
|
cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
|
|
cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);
|
|
|
|
cregs.c2misc=0 // CRTCV2 656 togg f0
|
|
+(0<<1) // CRTCV2 656 togg f0
|
|
+(0<<2) // CRTCV2 656 togg f0
|
|
+(0<<4) // CRTCV2 656 togg f1
|
|
+(0<<5) // CRTCV2 656 togg f1
|
|
+(0<<6) // CRTCV2 656 togg f1
|
|
+(0<<8) // Hsync active high
|
|
+(0<<9) // Vsync active high
|
|
// 16-27 c2vlinecomp - nevim co tam dat
|
|
;
|
|
cregs.c2offset=(regs.bespitch << 1);
|
|
|
|
cregs.c2pl2startadd0=regs.besa1corg;
|
|
// cregs.c2pl2startadd1=regs.besa2corg;
|
|
cregs.c2pl3startadd0=regs.besa1c3org;
|
|
// cregs.c2pl3startadd1=regs.besa2c3org;
|
|
|
|
cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from
|
|
|
|
cregs.c2spicstartadd0=0; // not used
|
|
// cregs.c2spicstartadd1=0; // not used
|
|
|
|
cregs.c2startadd0=regs.besa1org;
|
|
// cregs.c2startadd1=regs.besa2org;
|
|
|
|
cregs.c2subpiclut=0; //not used
|
|
|
|
cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
|
|
cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
|
|
#endif /* CRTC2 */
|
|
|
|
mga_vid_write_regs(0);
|
|
return(0);
|
|
}
|
|
|
|
static int mga_playback_on(void)
|
|
{
|
|
if (mga_verbose) printf("[mga] playback on\n");
|
|
|
|
vid_src_ready = 1;
|
|
if(vid_overlay_on)
|
|
{
|
|
regs.besctl |= 1;
|
|
mga_vid_write_regs(0);
|
|
}
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if (mga_irq != -1)
|
|
enable_irq();
|
|
#endif
|
|
mga_next_frame=0;
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int mga_playback_off(void)
|
|
{
|
|
if (mga_verbose) printf("[mga] playback off\n");
|
|
|
|
vid_src_ready = 0;
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if (mga_irq != -1)
|
|
disable_irq();
|
|
#endif
|
|
regs.besctl &= ~1;
|
|
regs.besglobctl &= ~(1<<6); /* UYVY format selected */
|
|
mga_vid_write_regs(0);
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int mga_probe(int verbose,int force)
|
|
{
|
|
pciinfo_t lst[MAX_PCI_DEVICES];
|
|
unsigned int i, num_pci;
|
|
int err;
|
|
|
|
if (verbose) printf("[mga] probe\n");
|
|
|
|
mga_verbose = verbose;
|
|
|
|
is_g400 = -1;
|
|
|
|
err = pci_scan(lst, &num_pci);
|
|
if (err)
|
|
{
|
|
printf("[mga] Error occurred during pci scan: %s\n", strerror(err));
|
|
return(err);
|
|
}
|
|
|
|
if (mga_verbose)
|
|
printf("[mga] found %d pci devices\n", num_pci);
|
|
|
|
for (i = 0; i < num_pci; i++)
|
|
{
|
|
if (mga_verbose > 1)
|
|
printf("[mga] pci[%d] vendor: %d device: %d\n",
|
|
i, lst[i].vendor, lst[i].device);
|
|
if (lst[i].vendor == VENDOR_MATROX)
|
|
{
|
|
if ((lst[i].command & PCI_COMMAND_IO) == 0)
|
|
{
|
|
printf("[mga] Device is disabled, ignoring\n");
|
|
continue;
|
|
}
|
|
switch(lst[i].device)
|
|
{
|
|
case DEVICE_MATROX_MGA_G550_AGP:
|
|
printf("[mga] Found MGA G550\n");
|
|
is_g400 = 1;
|
|
goto card_found;
|
|
case DEVICE_MATROX_MGA_G400_AGP:
|
|
printf("[mga] Found MGA G400/G450\n");
|
|
is_g400 = 1;
|
|
goto card_found;
|
|
case DEVICE_MATROX_MGA_G200_AGP:
|
|
printf("[mga] Found MGA G200 AGP\n");
|
|
is_g400 = 0;
|
|
goto card_found;
|
|
case DEVICE_MATROX_MGA_G200:
|
|
printf("[mga] Found MGA G200 PCI\n");
|
|
is_g400 = 0;
|
|
goto card_found;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (is_g400 == -1)
|
|
{
|
|
if (verbose) printf("[mga] Can't find chip\n");
|
|
return(ENXIO);
|
|
}
|
|
|
|
card_found:
|
|
probed = 1;
|
|
memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
|
|
|
|
mga_cap.device_id = pci_info.device; /* set device id in capabilites */
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int mga_init(void)
|
|
{
|
|
unsigned int card_option = 0;
|
|
int err;
|
|
|
|
if (mga_verbose) printf("[mga] init\n");
|
|
|
|
mga_vid_in_use = 0;
|
|
|
|
printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n");
|
|
#ifdef CRCT2
|
|
printf("Driver compiled with TV-out (second-head) support\n");
|
|
#endif
|
|
|
|
if (!probed)
|
|
{
|
|
printf("[mga] driver was not probed but is being initializing\n");
|
|
return(EINTR);
|
|
}
|
|
|
|
#ifdef MGA_PCICONFIG_MEMDETECT
|
|
pci_config_read(pci_info.bus, pci_info.card, pci_info.func,
|
|
0x40, 4, &card_option);
|
|
if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option,
|
|
(card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
|
|
#endif
|
|
|
|
if (mga_ram_size)
|
|
{
|
|
printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size);
|
|
}
|
|
else
|
|
{
|
|
#ifdef MGA_MEMORY_SIZE
|
|
mga_ram_size = MGA_MEMORY_SIZE;
|
|
printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
|
#else
|
|
if (is_g400)
|
|
{
|
|
switch((card_option>>10)&0x17)
|
|
{
|
|
// SDRAM:
|
|
case 0x00:
|
|
case 0x04: mga_ram_size = 16; break;
|
|
case 0x03: mga_ram_size = 32; break;
|
|
// SGRAM:
|
|
case 0x10:
|
|
case 0x14: mga_ram_size = 32; break;
|
|
case 0x11:
|
|
case 0x12: mga_ram_size = 16; break;
|
|
default:
|
|
mga_ram_size = 16;
|
|
printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch((card_option>>10)&0x17)
|
|
{
|
|
// case 0x10:
|
|
// case 0x13: mga_ram_size = 8; break;
|
|
default: mga_ram_size = 8;
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
// printf("List resources -----------\n");
|
|
for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
|
|
struct resource *res=&pci_dev->resource[temp];
|
|
if(res->flags){
|
|
int size=(1+res->end-res->start)>>20;
|
|
printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
|
|
if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
|
|
if(size>mga_ram_size && size<=64) mga_ram_size=size;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
|
|
#endif
|
|
}
|
|
|
|
if (mga_ram_size)
|
|
{
|
|
if ((mga_ram_size < 4) || (mga_ram_size > 64))
|
|
{
|
|
printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size);
|
|
return(EINVAL);
|
|
}
|
|
}
|
|
|
|
if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n",
|
|
pci_info.base1, pci_info.base0);
|
|
|
|
mga_mmio_base = map_phys_mem(pci_info.base1,0x4000);
|
|
mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024);
|
|
|
|
if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n",
|
|
mga_mmio_base, mga_irq, mga_mem_base);
|
|
err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB);
|
|
if(!err) printf("[mga] Set write-combining type of video memory\n");
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if (mga_irq != -1)
|
|
{
|
|
int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
|
|
if (tmp)
|
|
{
|
|
printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
|
|
mga_irq=-1;
|
|
}
|
|
else
|
|
{
|
|
printf("syncfb (mga): registered irq %d\n", mga_irq);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
printf("syncfb (mga): No valid irq was found\n");
|
|
mga_irq=-1;
|
|
}
|
|
#else
|
|
printf("syncfb (mga): IRQ disabled in mga_vid.c\n");
|
|
mga_irq=-1;
|
|
#endif
|
|
|
|
return(0);
|
|
}
|
|
|
|
static void mga_destroy(void)
|
|
{
|
|
if (mga_verbose) printf("[mga] destroy\n");
|
|
|
|
/* FIXME turn off BES */
|
|
vid_src_ready = 0;
|
|
regs.besctl &= ~1;
|
|
regs.besglobctl &= ~(1<<6); // UYVY format selected
|
|
// mga_config.colkey_on=0; //!!!
|
|
mga_vid_write_regs(1);
|
|
mga_vid_in_use = 0;
|
|
|
|
#ifdef MGA_ALLOW_IRQ
|
|
if (mga_irq != -1)
|
|
free_irq(mga_irq, &mga_irq);
|
|
#endif
|
|
|
|
if (mga_mmio_base)
|
|
unmap_phys_mem(mga_mmio_base, 0x4000);
|
|
if (mga_mem_base)
|
|
unmap_phys_mem(mga_mem_base, mga_ram_size);
|
|
return;
|
|
}
|
|
|
|
static int mga_query_fourcc(vidix_fourcc_t *to)
|
|
{
|
|
if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc);
|
|
|
|
switch(to->fourcc)
|
|
{
|
|
case IMGFMT_YV12:
|
|
case IMGFMT_IYUV:
|
|
case IMGFMT_I420:
|
|
case IMGFMT_YUY2:
|
|
case IMGFMT_UYVY:
|
|
break;
|
|
default:
|
|
to->depth = to->flags = 0;
|
|
return(ENOTSUP);
|
|
}
|
|
|
|
to->depth = VID_DEPTH_12BPP |
|
|
VID_DEPTH_15BPP | VID_DEPTH_16BPP |
|
|
VID_DEPTH_24BPP | VID_DEPTH_32BPP;
|
|
to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
|
|
return(0);
|
|
}
|
|
|
|
static int mga_get_caps(vidix_capability_t *to)
|
|
{
|
|
memcpy(to, &mga_cap, sizeof(vidix_capability_t));
|
|
return(0);
|
|
}
|
|
|
|
static int mga_get_gkeys(vidix_grkey_t *grkey)
|
|
{
|
|
memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t));
|
|
return(0);
|
|
}
|
|
|
|
static int mga_set_gkeys(const vidix_grkey_t *grkey)
|
|
{
|
|
memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t));
|
|
mga_vid_write_regs(0);
|
|
return(0);
|
|
}
|
|
|
|
static int mga_set_eq( const vidix_video_eq_t * eq)
|
|
{
|
|
/* contrast and brightness control isn't supported on G200 - alex */
|
|
if (!is_g400)
|
|
{
|
|
if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
|
|
return(ENOTSUP);
|
|
}
|
|
|
|
// only brightness&contrast are supported:
|
|
if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST)))
|
|
return(ENOTSUP);
|
|
|
|
//regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
|
|
// printf("LUMA = %08X \n",regs.beslumactl);
|
|
if (eq->cap & VEQ_CAP_BRIGHTNESS) {
|
|
regs.beslumactl &= 0xFFFF;
|
|
regs.beslumactl |= (eq->brightness*255/2000)<<16;
|
|
}
|
|
if (eq->cap & VEQ_CAP_CONTRAST) {
|
|
regs.beslumactl &= 0xFFFF0000;
|
|
regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF;
|
|
}
|
|
writel(regs.beslumactl,mga_mmio_base + BESLUMACTL);
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int mga_get_eq( vidix_video_eq_t * eq)
|
|
{
|
|
/* contrast and brightness control isn't supported on G200 - alex */
|
|
if (!is_g400)
|
|
{
|
|
if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n");
|
|
return(ENOTSUP);
|
|
}
|
|
|
|
// regs.beslumactl = readl(mga_mmio_base + BESLUMACTL);
|
|
|
|
eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128;
|
|
eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000;
|
|
eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;
|
|
|
|
printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast);
|
|
|
|
return(0);
|
|
}
|
|
|
|
#ifndef CRTC2
|
|
VDXDriver mga_drv = {
|
|
"mga",
|
|
#else
|
|
VDXDriver mga_crtc2_drv = {
|
|
"mga_crtc2",
|
|
#endif
|
|
NULL,
|
|
|
|
.probe = mga_probe,
|
|
.get_caps = mga_get_caps,
|
|
.query_fourcc = mga_query_fourcc,
|
|
.init = mga_init,
|
|
.destroy = mga_destroy,
|
|
.config_playback = mga_config_playback,
|
|
.playback_on = mga_playback_on,
|
|
.playback_off = mga_playback_off,
|
|
.frame_sel = mga_frame_select,
|
|
.get_eq = mga_get_eq,
|
|
.set_eq = mga_set_eq,
|
|
.get_gkey = mga_get_gkeys,
|
|
.set_gkey = mga_set_gkeys,
|
|
};
|