mirror of
https://github.com/mpv-player/mpv
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6445f83deb
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@11679 b3059339-0415-0410-9bf9-f77b7e298cf2
1561 lines
41 KiB
C
1561 lines
41 KiB
C
/**
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VIDIX driver for SiS 300 and 310/325 series chips.
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Copyright 2003 Jake Page, Sugar Media.
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Based on SiS Xv driver:
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Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi
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**/
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#include <errno.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <inttypes.h>
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#include <unistd.h>
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#include "../vidix.h"
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#include "../fourcc.h"
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#include "../../libdha/libdha.h"
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#include "../../libdha/pci_ids.h"
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#include "../../libdha/pci_names.h"
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#include "../../config.h"
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#include "sis_regs.h"
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#include "sis_defs.h"
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/** Random defines **/
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#define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */
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#define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */
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#define IMAGE_MIN_HEIGHT 24
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#define IMAGE_MAX_WIDTH 720
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#define IMAGE_MAX_HEIGHT 576
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#define IMAGE_MAX_WIDTH_M650 1920
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#define IMAGE_MAX_HEIGHT_M650 1080
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#define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */
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#define OVERLAY_MIN_HEIGHT 24
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#define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */
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#define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */
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#define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */
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#define VMODE_INTERLACED 0x1
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#define VMODE_DOUBLESCAN 0x2
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typedef struct {
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short x1, y1, x2, y2;
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} BoxRec;
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typedef struct {
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int pixelFormat;
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uint16_t pitch;
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uint16_t origPitch;
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uint8_t keyOP;
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uint16_t HUSF;
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uint16_t VUSF;
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uint8_t IntBit;
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uint8_t wHPre;
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uint16_t srcW;
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uint16_t srcH;
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BoxRec dstBox;
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uint32_t PSY;
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uint32_t PSV;
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uint32_t PSU;
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uint8_t bobEnable;
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uint8_t contrastCtrl;
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uint8_t contrastFactor;
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uint8_t lineBufSize;
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uint8_t(*VBlankActiveFunc) ();
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uint16_t SCREENheight;
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} SISOverlayRec, *SISOverlayPtr;
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/** static variable definitions **/
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static int sis_probed = 0;
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static pciinfo_t pci_info;
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unsigned int sis_verbose = 0;
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static void *sis_mem_base;
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/* static void *sis_reg_base; */
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unsigned short sis_iobase;
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unsigned int sis_vga_engine = UNKNOWN_VGA;
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static unsigned int sis_displaymode = DISPMODE_SINGLE1;
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static unsigned int sis_has_two_overlays = 0;
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static unsigned int sis_bridge_is_slave = 0;
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static unsigned int sis_shift_value = 1;
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static unsigned int sis_vmode = 0;
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unsigned int sis_vbflags = DISPTYPE_DISP1;
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unsigned int sis_overlay_on_crt1 = 1;
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unsigned int sis_crt1_off = -1;
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unsigned int sis_detected_crt2_devices;
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unsigned int sis_force_crt2_type = CRT2_DEFAULT;
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unsigned int sis_device_id = -1;
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static int sis_format;
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static int sis_Yoff = 0;
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static int sis_Voff = 0;
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static int sis_Uoff = 0;
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static int sis_screen_width = 640;
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static int sis_screen_height = 480;
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static int sis_frames[VID_PLAY_MAXFRAMES];
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static vidix_grkey_t sis_grkey;
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static vidix_capability_t sis_cap = {
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"SiS 300/310/325 Video Driver",
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"Jake Page",
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TYPE_OUTPUT,
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{0, 0, 0, 0},
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2048,
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2048,
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4,
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4,
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-1,
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FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
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VENDOR_SIS,
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-1,
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{0, 0, 0, 0}
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};
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vidix_video_eq_t sis_equal = {
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VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST,
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200, 0, 0, 0, 0, 0, 0, 0
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};
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static unsigned short sis_card_ids[] = {
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DEVICE_SIS_300,
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DEVICE_SIS_315H,
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DEVICE_SIS_315,
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DEVICE_SIS_315PRO,
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DEVICE_SIS_330,
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DEVICE_SIS_540_VGA,
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DEVICE_SIS_550_VGA,
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DEVICE_SIS_630_VGA,
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DEVICE_SIS_650_VGA
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};
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/** function declarations **/
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extern void sis_init_video_bridge();
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static void set_overlay(SISOverlayPtr pOverlay, int index);
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static void close_overlay();
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static void calc_scale_factor(SISOverlayPtr pOverlay,
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int index, int iscrt2);
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static void set_line_buf_size(SISOverlayPtr pOverlay);
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static void merge_line_buf(int enable);
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static void set_format(SISOverlayPtr pOverlay);
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static void set_colorkey();
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static void set_brightness(uint8_t brightness);
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static void set_contrast(uint8_t contrast);
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static void set_saturation(char saturation);
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static void set_hue(uint8_t hue);
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#if 0
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static void set_alpha(uint8_t alpha);
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#endif
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/* IO Port access functions */
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static uint8_t getvideoreg(uint8_t reg)
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{
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uint8_t ret;
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inSISIDXREG(SISVID, reg, ret);
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return (ret);
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}
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static void setvideoreg(uint8_t reg, uint8_t data)
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{
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outSISIDXREG(SISVID, reg, data);
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}
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static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask)
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{
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uint8_t old;
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inSISIDXREG(SISVID, reg, old);
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data = (data & mask) | (old & (~mask));
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outSISIDXREG(SISVID, reg, data);
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}
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static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask)
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{
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uint8_t old;
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inSISIDXREG(SISSR, reg, old);
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data = (data & mask) | (old & (~mask));
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outSISIDXREG(SISSR, reg, data);
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}
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/* vblank checking*/
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static uint8_t vblank_active_CRT1()
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{
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/* this may be too simplistic? */
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return (inSISREG(SISINPSTAT) & 0x08);
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}
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static uint8_t vblank_active_CRT2()
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{
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uint8_t ret;
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if (sis_vga_engine == SIS_315_VGA) {
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inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret);
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} else {
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inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret);
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}
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return ((ret & 0x02) ^ 0x02);
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}
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unsigned int vixGetVersion(void)
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{
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return (VIDIX_VERSION);
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}
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static int find_chip(unsigned chip_id)
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{
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unsigned i;
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for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) {
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if (chip_id == sis_card_ids[i])
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return i;
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}
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return -1;
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}
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int vixProbe(int verbose, int force)
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{
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pciinfo_t lst[MAX_PCI_DEVICES];
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unsigned i, num_pci;
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int err;
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sis_verbose = verbose;
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force = force;
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err = pci_scan(lst, &num_pci);
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if (err) {
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printf("[SiS] Error occurred during pci scan: %s\n", strerror(err));
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return err;
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} else {
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err = ENXIO;
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for (i = 0; i < num_pci; i++) {
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if (lst[i].vendor == VENDOR_SIS) {
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int idx;
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const char *dname;
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idx = find_chip(lst[i].device);
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if (idx == -1)
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continue;
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dname = pci_device_name(VENDOR_SIS, lst[i].device);
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dname = dname ? dname : "Unknown chip";
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if (sis_verbose > 0)
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printf("[SiS] Found chip: %s (0x%X)\n",
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dname, lst[i].device);
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sis_device_id = sis_cap.device_id = lst[i].device;
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err = 0;
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memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
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sis_has_two_overlays = 0;
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switch (sis_cap.device_id) {
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case DEVICE_SIS_300:
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case DEVICE_SIS_630_VGA:
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sis_has_two_overlays = 1;
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case DEVICE_SIS_540_VGA:
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sis_vga_engine = SIS_300_VGA;
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break;
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case DEVICE_SIS_330:
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case DEVICE_SIS_550_VGA:
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sis_has_two_overlays = 1;
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case DEVICE_SIS_315H:
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case DEVICE_SIS_315:
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case DEVICE_SIS_315PRO:
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case DEVICE_SIS_650_VGA:
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/* M650 & 651 have 2 overlays */
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/* JCP: I think this works, but not really tested yet */
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{
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unsigned char CR5F;
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unsigned char tempreg1, tempreg2;
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inSISIDXREG(SISCR, 0x5F, CR5F);
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CR5F &= 0xf0;
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andSISIDXREG(SISCR, 0x5c, 0x07);
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inSISIDXREG(SISCR, 0x5c, tempreg1);
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tempreg1 &= 0xf8;
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setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8);
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inSISIDXREG(SISCR, 0x5c, tempreg2);
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tempreg2 &= 0xf8;
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if ((!tempreg1) || (tempreg2)) {
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if (CR5F & 0x80) {
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sis_has_two_overlays = 1;
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}
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} else {
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sis_has_two_overlays = 1; /* ? */
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}
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if (sis_has_two_overlays) {
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if (sis_verbose > 0)
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printf
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("[SiS] detected M650/651 with 2 overlays\n");
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}
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}
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sis_vga_engine = SIS_315_VGA;
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break;
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default:
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/* should never get here */
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sis_vga_engine = UNKNOWN_VGA;
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break;
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}
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}
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}
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}
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if (err && sis_verbose) {
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printf("[SiS] Can't find chip\n");
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} else {
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sis_probed = 1;
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}
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return err;
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}
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int vixInit(void)
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{
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uint8_t sr_data, cr_data, cr_data2;
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char *env_overlay_crt;
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if (!sis_probed) {
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printf("[SiS] driver was not probed but is being initialized\n");
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return (EINTR);
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}
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/* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */
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/* map 16MB scary hack for now. */
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sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000);
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/* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */
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sis_iobase = pci_info.base2 & 0xFFFC;
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/* would like to use fb ioctl - or some other method - here to get
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current resolution. */
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inSISIDXREG(SISCR, 0x12, cr_data);
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inSISIDXREG(SISCR, 0x07, cr_data2);
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sis_screen_height =
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((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) |
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((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (sr_data & 0x02)
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<< 9)) + 1;
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inSISIDXREG(SISSR, 0x0b, sr_data);
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inSISIDXREG(SISCR, 0x01, cr_data);
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sis_screen_width = (((cr_data & 0xff) |
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((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8;
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inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data);
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if (sr_data & 0x20) /* interlaced mode */
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sis_vmode |= VMODE_INTERLACED;
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#if 0 /* getting back false data here... */
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/* CR9 bit 7 set = double scan active */
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inSISIDXREG(SISCR, 0x09, cr_data);
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if (cr_data & 0x40) {
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sis_vmode |= VMODE_DOUBLESCAN;
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}
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#endif
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/* JCP: eventually I'd like to replace this with a call to sisfb
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SISFB_GET_INFO ioctl to get video bridge info. Not for now,
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since it requires a very new and not widely distributed version. */
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sis_init_video_bridge();
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env_overlay_crt = getenv("VIDIX_CRT");
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if (env_overlay_crt) {
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int crt = atoi(env_overlay_crt);
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if (crt == 1 || crt == 2) {
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sis_overlay_on_crt1 = (crt == 1);
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if (sis_verbose > 0) {
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printf
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("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n",
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crt);
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}
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}
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}
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return 0;
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}
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void vixDestroy(void)
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{
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/* unmap_phys_mem(sis_reg_base, 0x20000); */
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/* JCP: see above, hence also a hack. */
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unmap_phys_mem(sis_mem_base, 0x1000000);
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}
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int vixGetCapability(vidix_capability_t * to)
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{
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memcpy(to, &sis_cap, sizeof(vidix_capability_t));
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return 0;
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}
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static int is_supported_fourcc(uint32_t fourcc)
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{
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switch (fourcc) {
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case IMGFMT_YV12:
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case IMGFMT_I420:
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case IMGFMT_UYVY:
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case IMGFMT_YUY2:
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case IMGFMT_RGB15:
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case IMGFMT_RGB16:
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return 1;
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default:
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return 0;
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}
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}
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int vixQueryFourcc(vidix_fourcc_t * to)
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{
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if (is_supported_fourcc(to->fourcc)) {
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to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP;
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to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
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return 0;
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} else
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to->depth = to->flags = 0;
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return ENOSYS;
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}
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static int bridge_in_slave_mode()
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{
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unsigned char usScratchP1_00;
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if (!(sis_vbflags & VB_VIDEOBRIDGE))
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return 0;
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inSISIDXREG(SISPART1, 0x00, usScratchP1_00);
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if (((sis_vga_engine == SIS_300_VGA)
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&& (usScratchP1_00 & 0xa0) == 0x20)
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|| ((sis_vga_engine == SIS_315_VGA)
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&& (usScratchP1_00 & 0x50) == 0x10)) {
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return 1;
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} else {
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return 0;
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}
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}
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/* This does not handle X dual head mode, since 1) vidix doesn't support it
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and 2) it doesn't make sense for other gfx drivers */
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static void set_dispmode()
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{
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sis_bridge_is_slave = 0;
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if (bridge_in_slave_mode())
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sis_bridge_is_slave = 1;
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if ((sis_vbflags & VB_DISPMODE_MIRROR) ||
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(sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) {
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if (sis_has_two_overlays)
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sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */
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else if (!sis_overlay_on_crt1)
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sis_displaymode = DISPMODE_SINGLE2;
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else
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sis_displaymode = DISPMODE_SINGLE1;
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} else {
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if (sis_vbflags & DISPTYPE_DISP1) {
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sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */
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} else {
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sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */
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}
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}
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}
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static void set_disptype_regs()
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{
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switch (sis_displaymode) {
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case DISPMODE_SINGLE1: /* TW: CRT1 only */
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if (sis_verbose > 2) {
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printf("[SiS] Setting up overlay on CRT1\n");
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}
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if (sis_has_two_overlays) {
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setsrregmask(0x06, 0x00, 0xc0);
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setsrregmask(0x32, 0x00, 0xc0);
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|
} else {
|
|
setsrregmask(0x06, 0x00, 0xc0);
|
|
setsrregmask(0x32, 0x00, 0xc0);
|
|
}
|
|
break;
|
|
case DISPMODE_SINGLE2: /* TW: CRT2 only */
|
|
if (sis_verbose > 2) {
|
|
printf("[SiS] Setting up overlay on CRT2\n");
|
|
}
|
|
if (sis_has_two_overlays) {
|
|
setsrregmask(0x06, 0x80, 0xc0);
|
|
setsrregmask(0x32, 0x80, 0xc0);
|
|
} else {
|
|
setsrregmask(0x06, 0x40, 0xc0);
|
|
setsrregmask(0x32, 0x40, 0xc0);
|
|
}
|
|
break;
|
|
case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */
|
|
default:
|
|
if (sis_verbose > 2) {
|
|
printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n");
|
|
}
|
|
setsrregmask(0x06, 0x80, 0xc0);
|
|
setsrregmask(0x32, 0x80, 0xc0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void init_overlay()
|
|
{
|
|
/* Initialize first overlay (CRT1) */
|
|
|
|
/* Write-enable video registers */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81);
|
|
|
|
/* Disable overlay */
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
|
|
|
|
/* Disable bobEnable */
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
|
|
|
|
/* Reset scale control and contrast */
|
|
setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
|
|
setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
|
|
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
|
|
setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
|
|
setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
|
|
setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
|
|
setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
|
|
setvideoreg(Index_VI_Play_Threshold_High, 0x00);
|
|
|
|
/* may not want to init these here, could already be set to other
|
|
values by app? */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
|
|
setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
|
|
setvideoreg(Index_VI_Brightness, 0x20);
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_Hue, 0x00);
|
|
setvideoreg(Index_VI_Saturation, 0x00);
|
|
}
|
|
|
|
/* Initialize second overlay (CRT2) */
|
|
if (sis_has_two_overlays) {
|
|
/* Write-enable video registers */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81);
|
|
|
|
/* Disable overlay */
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
|
|
|
|
/* Disable bobEnable */
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
|
|
|
|
/* Reset scale control and contrast */
|
|
setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
|
|
setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
|
|
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
|
|
setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
|
|
setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
|
|
setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
|
|
setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
|
|
setvideoreg(Index_VI_Play_Threshold_High, 0x00);
|
|
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
|
|
setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
|
|
setvideoreg(Index_VI_Brightness, 0x20);
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_Hue, 0x00);
|
|
setvideoreg(Index_VI_Saturation, 0x00);
|
|
}
|
|
}
|
|
}
|
|
|
|
int vixConfigPlayback(vidix_playback_t * info)
|
|
{
|
|
SISOverlayRec overlay;
|
|
int srcOffsetX = 0, srcOffsetY = 0;
|
|
int sx, sy;
|
|
int index = 0, iscrt2 = 0;
|
|
int total_size;
|
|
|
|
short src_w, drw_w;
|
|
short src_h, drw_h;
|
|
short src_x, drw_x;
|
|
short src_y, drw_y;
|
|
long dga_offset;
|
|
int pitch;
|
|
unsigned int i;
|
|
|
|
if (!is_supported_fourcc(info->fourcc))
|
|
return -1;
|
|
|
|
/* set chipset/engine.dependent config info */
|
|
/* which CRT to use, etc.? */
|
|
switch (sis_vga_engine) {
|
|
case SIS_315_VGA:
|
|
sis_shift_value = 1;
|
|
sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE;
|
|
break;
|
|
case SIS_300_VGA:
|
|
default:
|
|
sis_shift_value = 2;
|
|
break;
|
|
}
|
|
|
|
sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */
|
|
set_dispmode();
|
|
|
|
set_disptype_regs();
|
|
|
|
init_overlay();
|
|
|
|
/* get basic dimension info */
|
|
src_x = info->src.x;
|
|
src_y = info->src.y;
|
|
src_w = info->src.w;
|
|
src_h = info->src.h;
|
|
|
|
drw_x = info->dest.x;
|
|
drw_y = info->dest.y;
|
|
drw_w = info->dest.w;
|
|
drw_h = info->dest.h;
|
|
|
|
switch (info->fourcc) {
|
|
case IMGFMT_YV12:
|
|
case IMGFMT_I420:
|
|
pitch = (src_w + 7) & ~7;
|
|
total_size = (pitch * src_h * 3) >> 1;
|
|
break;
|
|
case IMGFMT_YUY2:
|
|
case IMGFMT_UYVY:
|
|
case IMGFMT_RGB15:
|
|
case IMGFMT_RGB16:
|
|
pitch = ((src_w << 1) + 3) & ~3;
|
|
total_size = pitch * src_h;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
/* "allocate" memory for overlay! */
|
|
/* start at 8MB = sisfb's "dri reserved space" -
|
|
really shouldn't hardcode though */
|
|
/* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely
|
|
allocate "video heap" memory... */
|
|
dga_offset = 0x800000;
|
|
|
|
/* use 7MB for now. need to calc/get real info from sisfb? */
|
|
/* this can result in a LOT of frames - probably not necessary */
|
|
info->num_frames = 0x700000 / (total_size * 2);
|
|
if (info->num_frames > VID_PLAY_MAXFRAMES)
|
|
info->num_frames = VID_PLAY_MAXFRAMES;
|
|
|
|
info->dga_addr = sis_mem_base + dga_offset;
|
|
info->dest.pitch.y = 16;
|
|
info->dest.pitch.u = 16;
|
|
info->dest.pitch.v = 16;
|
|
info->offset.y = 0;
|
|
info->offset.u = 0;
|
|
info->offset.v = 0;
|
|
info->frame_size = (total_size * 2); /* why times 2 ? */
|
|
for (i = 0; i < info->num_frames; i++) {
|
|
info->offsets[i] = info->frame_size * i;
|
|
/* save ptrs to mem buffers */
|
|
sis_frames[i] = (dga_offset + info->offsets[i]);
|
|
}
|
|
|
|
memset(&overlay, 0, sizeof(overlay));
|
|
overlay.pixelFormat = sis_format = info->fourcc;
|
|
overlay.pitch = overlay.origPitch = pitch;
|
|
|
|
|
|
overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ?
|
|
VI_ROP_DestKey : VI_ROP_Always);
|
|
|
|
overlay.bobEnable = 0x00;
|
|
|
|
overlay.SCREENheight = sis_screen_height;
|
|
|
|
/* probably will not support X virtual screen > phys very well? */
|
|
overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */
|
|
overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */
|
|
overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */
|
|
overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */
|
|
|
|
if ((overlay.dstBox.x1 > overlay.dstBox.x2) ||
|
|
(overlay.dstBox.y1 > overlay.dstBox.y2))
|
|
return -1;
|
|
|
|
if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0))
|
|
return -1;
|
|
|
|
if (overlay.dstBox.x1 < 0) {
|
|
srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w;
|
|
overlay.dstBox.x1 = 0;
|
|
}
|
|
if (overlay.dstBox.y1 < 0) {
|
|
srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h;
|
|
overlay.dstBox.y1 = 0;
|
|
}
|
|
|
|
switch (info->fourcc) {
|
|
case IMGFMT_YV12:
|
|
info->dest.pitch.y = 16;
|
|
sx = (src_x + srcOffsetX) & ~7;
|
|
sy = (src_y + srcOffsetY) & ~1;
|
|
info->offset.y = sis_Yoff = sx + sy * pitch;
|
|
/* JCP: NOTE reversed u & v here! Not sure why this is needed.
|
|
maybe mplayer & sis define U & V differently?? */
|
|
info->offset.u = sis_Voff =
|
|
src_h * pitch + ((sx + sy * pitch / 2) >> 1);
|
|
info->offset.v = sis_Uoff =
|
|
src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
|
|
|
|
overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
|
|
overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
|
|
overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
|
|
break;
|
|
case IMGFMT_I420:
|
|
sx = (src_x + srcOffsetX) & ~7;
|
|
sy = (src_y + srcOffsetY) & ~1;
|
|
info->offset.y = sis_Yoff = sx + sy * pitch;
|
|
/* JCP: see above... */
|
|
info->offset.u = sis_Voff =
|
|
src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
|
|
info->offset.v = sis_Uoff =
|
|
src_h * pitch + ((sx + sy * pitch / 2) >> 1);
|
|
|
|
overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
|
|
overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
|
|
overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
|
|
break;
|
|
case IMGFMT_YUY2:
|
|
case IMGFMT_UYVY:
|
|
case IMGFMT_RGB16:
|
|
case IMGFMT_RGB15:
|
|
default:
|
|
sx = (src_x + srcOffsetX) & ~1;
|
|
sy = (src_y + srcOffsetY);
|
|
info->offset.y = sis_Yoff = sx * 2 + sy * pitch;
|
|
|
|
overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
|
|
break;
|
|
}
|
|
|
|
/* FIXME: is it possible that srcW < 0? */
|
|
overlay.srcW = src_w - (sx - src_x);
|
|
overlay.srcH = src_h - (sy - src_y);
|
|
|
|
/* JCP: what to do about this? */
|
|
#if 0
|
|
if ((pPriv->oldx1 != overlay.dstBox.x1) ||
|
|
(pPriv->oldx2 != overlay.dstBox.x2) ||
|
|
(pPriv->oldy1 != overlay.dstBox.y1) ||
|
|
(pPriv->oldy2 != overlay.dstBox.y2)) {
|
|
pPriv->mustwait = 1;
|
|
pPriv->oldx1 = overlay.dstBox.x1;
|
|
pPriv->oldx2 = overlay.dstBox.x2;
|
|
pPriv->oldy1 = overlay.dstBox.y1;
|
|
pPriv->oldy2 = overlay.dstBox.y2;
|
|
}
|
|
#endif
|
|
|
|
/* set merge line buffer */
|
|
merge_line_buf(overlay.srcW > 384);
|
|
|
|
/* calculate line buffer length */
|
|
set_line_buf_size(&overlay);
|
|
|
|
if (sis_displaymode == DISPMODE_SINGLE2) {
|
|
if (sis_has_two_overlays) {
|
|
/* TW: On chips with two overlays we use
|
|
* overlay 2 for CRT2 */
|
|
index = 1;
|
|
iscrt2 = 1;
|
|
} else {
|
|
/* TW: On chips with only one overlay we
|
|
* use that only overlay for CRT2 */
|
|
index = 0;
|
|
iscrt2 = 1;
|
|
}
|
|
overlay.VBlankActiveFunc = vblank_active_CRT2;
|
|
/* overlay.GetScanLineFunc = get_scanline_CRT2; */
|
|
} else {
|
|
index = 0;
|
|
iscrt2 = 0;
|
|
overlay.VBlankActiveFunc = vblank_active_CRT1;
|
|
/* overlay.GetScanLineFunc = get_scanline_CRT1; */
|
|
}
|
|
|
|
/* calc scale factor (to use below) */
|
|
calc_scale_factor(&overlay, index, iscrt2);
|
|
|
|
/* Select video1 (used for CRT1) or video2 (used for CRT2) */
|
|
setvideoregmask(Index_VI_Control_Misc2, index, 0x01);
|
|
|
|
set_format(&overlay);
|
|
|
|
set_colorkey();
|
|
|
|
vixPlaybackSetEq(&sis_equal);
|
|
|
|
/* set up video overlay registers */
|
|
set_overlay(&overlay, index);
|
|
|
|
/* prevent badness if bits are not at default setting */
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01);
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04);
|
|
|
|
/* JCP: Xv driver implementation loops back over above code to
|
|
setup mirror CRT2 */
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vixPlaybackOn(void)
|
|
{
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02);
|
|
return 0;
|
|
}
|
|
|
|
int vixPlaybackOff(void)
|
|
{
|
|
unsigned char sridx, cridx;
|
|
sridx = inSISREG(SISSR);
|
|
cridx = inSISREG(SISCR);
|
|
close_overlay();
|
|
outSISREG(SISSR, sridx);
|
|
outSISREG(SISCR, cridx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vixPlaybackFrameSelect(unsigned int frame)
|
|
{
|
|
uint8_t data;
|
|
int index = 0;
|
|
uint32_t PSY;
|
|
|
|
if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) {
|
|
index = 1;
|
|
}
|
|
|
|
PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value;
|
|
|
|
/* Unlock address registers */
|
|
data = getvideoreg(Index_VI_Control_Misc1);
|
|
setvideoreg(Index_VI_Control_Misc1, data | 0x20);
|
|
/* TEST: Is this required? */
|
|
setvideoreg(Index_VI_Control_Misc1, data | 0x20);
|
|
/* TEST end */
|
|
/* TEST: Is this required? */
|
|
if (sis_vga_engine == SIS_315_VGA)
|
|
setvideoreg(Index_VI_Control_Misc3, 0x00);
|
|
/* TEST end */
|
|
|
|
/* set Y start address */
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY));
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8));
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16));
|
|
/* set 310/325 series overflow bits for Y plane */
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_Y_Buf_Start_Over,
|
|
((uint8_t) ((PSY) >> 24) & 0x01));
|
|
}
|
|
|
|
/* Set U/V data if using plane formats */
|
|
if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) {
|
|
|
|
uint32_t PSU, PSV;
|
|
|
|
PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value;
|
|
PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value;
|
|
|
|
/* set U/V start address */
|
|
setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
|
|
setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
|
|
setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
|
|
|
|
setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
|
|
setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
|
|
setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
|
|
|
|
/* 310/325 series overflow bits */
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_U_Buf_Start_Over,
|
|
((uint8_t) (PSU >> 24) & 0x01));
|
|
setvideoreg(Index_VI_V_Buf_Start_Over,
|
|
((uint8_t) (PSV >> 24) & 0x01));
|
|
}
|
|
}
|
|
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
/* Trigger register copy for 310 series */
|
|
setvideoreg(Index_VI_Control_Misc3, 1 << index);
|
|
}
|
|
|
|
/* Lock the address registers */
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vixGetGrKeys(vidix_grkey_t * grkey)
|
|
{
|
|
memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t));
|
|
return 0;
|
|
}
|
|
|
|
int vixSetGrKeys(const vidix_grkey_t * grkey)
|
|
{
|
|
memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t));
|
|
set_colorkey();
|
|
return 0;
|
|
}
|
|
|
|
int vixPlaybackGetEq(vidix_video_eq_t * eq)
|
|
{
|
|
memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t));
|
|
return 0;
|
|
}
|
|
|
|
int vixPlaybackSetEq(const vidix_video_eq_t * eq)
|
|
{
|
|
int br, sat, cr, hue;
|
|
if (eq->cap & VEQ_CAP_BRIGHTNESS)
|
|
sis_equal.brightness = eq->brightness;
|
|
if (eq->cap & VEQ_CAP_CONTRAST)
|
|
sis_equal.contrast = eq->contrast;
|
|
if (eq->cap & VEQ_CAP_SATURATION)
|
|
sis_equal.saturation = eq->saturation;
|
|
if (eq->cap & VEQ_CAP_HUE)
|
|
sis_equal.hue = eq->hue;
|
|
if (eq->cap & VEQ_CAP_RGB_INTENSITY) {
|
|
sis_equal.red_intensity = eq->red_intensity;
|
|
sis_equal.green_intensity = eq->green_intensity;
|
|
sis_equal.blue_intensity = eq->blue_intensity;
|
|
}
|
|
sis_equal.flags = eq->flags;
|
|
|
|
cr = (sis_equal.contrast + 1000) * 7 / 2000;
|
|
if (cr < 0)
|
|
cr = 0;
|
|
if (cr > 7)
|
|
cr = 7;
|
|
|
|
br = sis_equal.brightness * 127 / 1000;
|
|
if (br < -128)
|
|
br = -128;
|
|
if (br > 127)
|
|
br = 127;
|
|
|
|
sat = (sis_equal.saturation * 7) / 1000;
|
|
if (sat < -7)
|
|
sat = -7;
|
|
if (sat > 7)
|
|
sat = 7;
|
|
|
|
hue = sis_equal.hue * 7 / 1000;
|
|
if (hue < -8)
|
|
hue = -8;
|
|
if (hue > 7)
|
|
hue = 7;
|
|
|
|
set_brightness(br);
|
|
set_contrast(cr);
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
set_saturation(sat);
|
|
set_hue(hue);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void set_overlay(SISOverlayPtr pOverlay, int index)
|
|
{
|
|
uint16_t pitch = 0;
|
|
uint8_t h_over = 0, v_over = 0;
|
|
uint16_t top, bottom, left, right;
|
|
uint16_t screenX = sis_screen_width;
|
|
uint16_t screenY = sis_screen_height;
|
|
uint8_t data;
|
|
uint32_t watchdog;
|
|
|
|
top = pOverlay->dstBox.y1;
|
|
bottom = pOverlay->dstBox.y2;
|
|
if (bottom > screenY) {
|
|
bottom = screenY;
|
|
}
|
|
|
|
left = pOverlay->dstBox.x1;
|
|
right = pOverlay->dstBox.x2;
|
|
if (right > screenX) {
|
|
right = screenX;
|
|
}
|
|
|
|
/* JCP: these aren't really tested... */
|
|
/* TW: DoubleScan modes require Y coordinates * 2 */
|
|
if (sis_vmode & VMODE_DOUBLESCAN) {
|
|
top <<= 1;
|
|
bottom <<= 1;
|
|
}
|
|
/* TW: Interlace modes require Y coordinates / 2 */
|
|
if (sis_vmode & VMODE_INTERLACED) {
|
|
top >>= 1;
|
|
bottom >>= 1;
|
|
}
|
|
|
|
h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0));
|
|
v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0));
|
|
|
|
pitch = pOverlay->pitch >> sis_shift_value;
|
|
|
|
/* set line buffer size */
|
|
setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize);
|
|
|
|
/* set color key mode */
|
|
setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F);
|
|
|
|
/* TW: We don't have to wait for vertical retrace in all cases */
|
|
/* JCP: be safe for now. */
|
|
if (1 /*pPriv->mustwait */ ) {
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (pOverlay->VBlankActiveFunc() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!pOverlay->VBlankActiveFunc()) && --watchdog);
|
|
if (!watchdog && sis_verbose > 0) {
|
|
printf("[SiS]: timed out waiting for vertical retrace\n");
|
|
}
|
|
}
|
|
|
|
/* Unlock address registers */
|
|
data = getvideoreg(Index_VI_Control_Misc1);
|
|
setvideoreg(Index_VI_Control_Misc1, data | 0x20);
|
|
/* TEST: Is this required? */
|
|
setvideoreg(Index_VI_Control_Misc1, data | 0x20);
|
|
/* TEST end */
|
|
|
|
/* TEST: Is this required? */
|
|
if (sis_vga_engine == SIS_315_VGA)
|
|
setvideoreg(Index_VI_Control_Misc3, 0x00);
|
|
/* TEST end */
|
|
|
|
/* Set Y buf pitch */
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch));
|
|
setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
|
|
(uint8_t) (pitch >> 8), 0x0f);
|
|
|
|
/* Set Y start address */
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY));
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle,
|
|
(uint8_t) ((pOverlay->PSY) >> 8));
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Start_High,
|
|
(uint8_t) ((pOverlay->PSY) >> 16));
|
|
|
|
/* set 310/325 series overflow bits for Y plane */
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High,
|
|
(uint8_t) (pitch >> 12));
|
|
setvideoreg(Index_VI_Y_Buf_Start_Over,
|
|
((uint8_t) ((pOverlay->PSY) >> 24) & 0x01));
|
|
}
|
|
|
|
/* Set U/V data if using plane formats */
|
|
if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
|
|
(pOverlay->pixelFormat == IMGFMT_I420)) {
|
|
|
|
uint32_t PSU, PSV;
|
|
|
|
PSU = pOverlay->PSU;
|
|
PSV = pOverlay->PSV;
|
|
|
|
/* Set U/V pitch */
|
|
setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low,
|
|
(uint8_t) (pitch >> 1));
|
|
setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
|
|
(uint8_t) (pitch >> 5), 0xf0);
|
|
|
|
/* set U/V start address */
|
|
setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
|
|
setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
|
|
setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
|
|
|
|
setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
|
|
setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
|
|
setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
|
|
|
|
/* 310/325 series overflow bits */
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High,
|
|
(uint8_t) (pitch >> 13));
|
|
setvideoreg(Index_VI_U_Buf_Start_Over,
|
|
((uint8_t) (PSU >> 24) & 0x01));
|
|
setvideoreg(Index_VI_V_Buf_Start_Over,
|
|
((uint8_t) (PSV >> 24) & 0x01));
|
|
}
|
|
}
|
|
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
/* Trigger register copy for 310 series */
|
|
setvideoreg(Index_VI_Control_Misc3, 1 << index);
|
|
}
|
|
|
|
/* set scale factor */
|
|
setvideoreg(Index_VI_Hor_Post_Up_Scale_Low,
|
|
(uint8_t) (pOverlay->HUSF));
|
|
setvideoreg(Index_VI_Hor_Post_Up_Scale_High,
|
|
(uint8_t) ((pOverlay->HUSF) >> 8));
|
|
setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF));
|
|
setvideoreg(Index_VI_Ver_Up_Scale_High,
|
|
(uint8_t) ((pOverlay->VUSF) >> 8));
|
|
|
|
setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3)
|
|
| (pOverlay->wHPre), 0x7f);
|
|
|
|
/* set destination window position */
|
|
setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left);
|
|
setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right);
|
|
setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over);
|
|
|
|
setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top);
|
|
setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom);
|
|
setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over);
|
|
|
|
setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a);
|
|
|
|
/* Lock the address registers */
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
|
|
}
|
|
|
|
|
|
/* TW: Overlay MUST NOT be switched off while beam is over it */
|
|
static void close_overlay()
|
|
{
|
|
uint32_t watchdog;
|
|
|
|
if ((sis_displaymode == DISPMODE_SINGLE2) ||
|
|
(sis_displaymode == DISPMODE_MIRROR)) {
|
|
if (sis_has_two_overlays) {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT2() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT2()) && --watchdog);
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT2() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT2()) && --watchdog);
|
|
} else if (sis_displaymode == DISPMODE_SINGLE2) {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT1() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT1()) && --watchdog);
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT1() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT1()) && --watchdog);
|
|
}
|
|
}
|
|
if ((sis_displaymode == DISPMODE_SINGLE1) ||
|
|
(sis_displaymode == DISPMODE_MIRROR)) {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT1() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT1()) && --watchdog);
|
|
setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while (vblank_active_CRT1() && --watchdog);
|
|
watchdog = WATCHDOG_DELAY;
|
|
while ((!vblank_active_CRT1()) && --watchdog);
|
|
}
|
|
}
|
|
|
|
|
|
static void
|
|
calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2)
|
|
{
|
|
uint32_t i = 0, mult = 0;
|
|
int flag = 0;
|
|
|
|
int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1;
|
|
int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1;
|
|
int srcW = pOverlay->srcW;
|
|
int srcH = pOverlay->srcH;
|
|
/* uint16_t LCDheight = pSiS->LCDheight; */
|
|
int srcPitch = pOverlay->origPitch;
|
|
int origdstH = dstH;
|
|
|
|
/* get rid of warnings for now */
|
|
index = index;
|
|
iscrt2 = iscrt2;
|
|
|
|
#if 0 /* JCP: don't bother with this for now. */
|
|
/* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */
|
|
if (pSiS->VBFlags & CRT2_LCD) {
|
|
if (sis_bridge_is_slave) {
|
|
if (pSiS->VBFlags & VB_LVDS) {
|
|
dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
|
|
} else if ((sis_vga_engine == SIS_300_VGA) &&
|
|
(pSiS->
|
|
VBFlags & (VB_301B | VB_302B | VB_301LV |
|
|
VB_302LV))) {
|
|
dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
|
|
}
|
|
} else if (iscrt2) {
|
|
if (pSiS->VBFlags & VB_LVDS) {
|
|
dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
|
|
if (sis_displaymode == DISPMODE_MIRROR)
|
|
flag = 1;
|
|
} else if ((sis_vga_engine == SIS_300_VGA) &&
|
|
(pSiS->
|
|
VBFlags & (VB_301B | VB_302B | VB_301LV |
|
|
VB_302LV))) {
|
|
dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
|
|
if (sis_displaymode == DISPMODE_MIRROR)
|
|
flag = 1;
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* TW: For double scan modes, we need to double the height
|
|
* (Perhaps we also need to scale LVDS, but I'm not sure.)
|
|
* On 310/325 series, we need to double the width as well.
|
|
* Interlace mode vice versa.
|
|
*/
|
|
if (sis_vmode & VMODE_DOUBLESCAN) {
|
|
dstH = origdstH << 1;
|
|
flag = 0;
|
|
if (sis_vga_engine == SIS_315_VGA) {
|
|
dstW <<= 1;
|
|
}
|
|
}
|
|
if (sis_vmode & VMODE_INTERLACED) {
|
|
dstH = origdstH >> 1;
|
|
flag = 0;
|
|
}
|
|
|
|
if (dstW < OVERLAY_MIN_WIDTH)
|
|
dstW = OVERLAY_MIN_WIDTH;
|
|
if (dstW == srcW) {
|
|
pOverlay->HUSF = 0x00;
|
|
pOverlay->IntBit = 0x05;
|
|
pOverlay->wHPre = 0;
|
|
} else if (dstW > srcW) {
|
|
dstW += 2;
|
|
pOverlay->HUSF = (srcW << 16) / dstW;
|
|
pOverlay->IntBit = 0x04;
|
|
pOverlay->wHPre = 0;
|
|
} else {
|
|
int tmpW = dstW;
|
|
|
|
/* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the
|
|
pitch isn't a multiple of 256.
|
|
TODO: Test this on the 310/325 series!
|
|
*/
|
|
if ((srcPitch % 256) || (srcPitch < 256)) {
|
|
if (((dstW * 1000) / srcW) < 125)
|
|
dstW = tmpW = ((srcW * 125) / 1000) + 1;
|
|
}
|
|
|
|
i = 0;
|
|
pOverlay->IntBit = 0x01;
|
|
while (srcW >= tmpW) {
|
|
tmpW <<= 1;
|
|
i++;
|
|
}
|
|
pOverlay->wHPre = (uint8_t) (i - 1);
|
|
dstW <<= (i - 1);
|
|
if ((srcW % dstW))
|
|
pOverlay->HUSF = ((srcW - dstW) << 16) / dstW;
|
|
else
|
|
pOverlay->HUSF = 0x00;
|
|
}
|
|
|
|
if (dstH < OVERLAY_MIN_HEIGHT)
|
|
dstH = OVERLAY_MIN_HEIGHT;
|
|
if (dstH == srcH) {
|
|
pOverlay->VUSF = 0x00;
|
|
pOverlay->IntBit |= 0x0A;
|
|
} else if (dstH > srcH) {
|
|
dstH += 0x02;
|
|
pOverlay->VUSF = (srcH << 16) / dstH;
|
|
pOverlay->IntBit |= 0x08;
|
|
} else {
|
|
uint32_t realI;
|
|
|
|
i = realI = srcH / dstH;
|
|
pOverlay->IntBit |= 0x02;
|
|
|
|
if (i < 2) {
|
|
pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
|
|
/* TW: Needed for LCD-scaling modes */
|
|
if ((flag) && (mult = (srcH / origdstH)) >= 2)
|
|
pOverlay->pitch /= mult;
|
|
} else {
|
|
#if 0
|
|
if (((pOverlay->bobEnable & 0x08) == 0x00) &&
|
|
(((srcPitch * i) >> 2) > 0xFFF)) {
|
|
pOverlay->bobEnable |= 0x08;
|
|
srcPitch >>= 1;
|
|
}
|
|
#endif
|
|
if (((srcPitch * i) >> 2) > 0xFFF) {
|
|
i = (0xFFF * 2 / srcPitch);
|
|
pOverlay->VUSF = 0xFFFF;
|
|
} else {
|
|
dstH = i * dstH;
|
|
if (srcH % dstH)
|
|
pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
|
|
else
|
|
pOverlay->VUSF = 0x00;
|
|
}
|
|
/* set video frame buffer offset */
|
|
pOverlay->pitch = (uint16_t) (srcPitch * i);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void set_line_buf_size(SISOverlayPtr pOverlay)
|
|
{
|
|
uint8_t preHIDF;
|
|
uint32_t i;
|
|
uint32_t line = pOverlay->srcW;
|
|
|
|
if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
|
|
(pOverlay->pixelFormat == IMGFMT_I420)) {
|
|
preHIDF = pOverlay->wHPre & 0x07;
|
|
switch (preHIDF) {
|
|
case 3:
|
|
if ((line & 0xffffff00) == line)
|
|
i = (line >> 8);
|
|
else
|
|
i = (line >> 8) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i * 32 - 1);
|
|
break;
|
|
case 4:
|
|
if ((line & 0xfffffe00) == line)
|
|
i = (line >> 9);
|
|
else
|
|
i = (line >> 9) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i * 64 - 1);
|
|
break;
|
|
case 5:
|
|
if ((line & 0xfffffc00) == line)
|
|
i = (line >> 10);
|
|
else
|
|
i = (line >> 10) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i * 128 - 1);
|
|
break;
|
|
case 6:
|
|
if ((line & 0xfffff800) == line)
|
|
i = (line >> 11);
|
|
else
|
|
i = (line >> 11) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i * 256 - 1);
|
|
break;
|
|
default:
|
|
if ((line & 0xffffff80) == line)
|
|
i = (line >> 7);
|
|
else
|
|
i = (line >> 7) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i * 16 - 1);
|
|
break;
|
|
}
|
|
} else { /* YUV2, UYVY */
|
|
if ((line & 0xffffff8) == line)
|
|
i = (line >> 3);
|
|
else
|
|
i = (line >> 3) + 1;
|
|
pOverlay->lineBufSize = (uint8_t) (i - 1);
|
|
}
|
|
}
|
|
|
|
static void merge_line_buf(int enable)
|
|
{
|
|
if (enable) {
|
|
switch (sis_displaymode) {
|
|
case DISPMODE_SINGLE1:
|
|
if (sis_has_two_overlays) {
|
|
/* dual line merge */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
} else {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
}
|
|
break;
|
|
case DISPMODE_SINGLE2:
|
|
if (sis_has_two_overlays) {
|
|
/* line merge */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
|
|
} else {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
}
|
|
break;
|
|
case DISPMODE_MIRROR:
|
|
default:
|
|
/* line merge */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
|
|
if (sis_has_two_overlays) {
|
|
/* line merge */
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
|
|
}
|
|
break;
|
|
}
|
|
} else {
|
|
switch (sis_displaymode) {
|
|
case DISPMODE_SINGLE1:
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
break;
|
|
case DISPMODE_SINGLE2:
|
|
if (sis_has_two_overlays) {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
} else {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
}
|
|
break;
|
|
case DISPMODE_MIRROR:
|
|
default:
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
if (sis_has_two_overlays) {
|
|
setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
|
|
setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
static void set_format(SISOverlayPtr pOverlay)
|
|
{
|
|
uint8_t fmt;
|
|
|
|
switch (pOverlay->pixelFormat) {
|
|
case IMGFMT_YV12:
|
|
case IMGFMT_I420:
|
|
fmt = 0x0c;
|
|
break;
|
|
case IMGFMT_YUY2:
|
|
fmt = 0x28;
|
|
break;
|
|
case IMGFMT_UYVY:
|
|
fmt = 0x08;
|
|
break;
|
|
case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */
|
|
fmt = 0x00;
|
|
break;
|
|
case IMGFMT_RGB16:
|
|
fmt = 0x10;
|
|
break;
|
|
default:
|
|
fmt = 0x00;
|
|
break;
|
|
}
|
|
setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c);
|
|
}
|
|
|
|
static void set_colorkey()
|
|
{
|
|
uint8_t r, g, b;
|
|
|
|
b = (uint8_t) sis_grkey.ckey.blue;
|
|
g = (uint8_t) sis_grkey.ckey.green;
|
|
r = (uint8_t) sis_grkey.ckey.red;
|
|
|
|
/* set color key mode */
|
|
setvideoregmask(Index_VI_Key_Overlay_OP,
|
|
sis_grkey.ckey.op == CKEY_TRUE ?
|
|
VI_ROP_DestKey : VI_ROP_Always, 0x0F);
|
|
|
|
/* set colorkey values */
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b);
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g);
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r);
|
|
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b);
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g);
|
|
setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r);
|
|
}
|
|
|
|
static void set_brightness(uint8_t brightness)
|
|
{
|
|
setvideoreg(Index_VI_Brightness, brightness);
|
|
}
|
|
|
|
static void set_contrast(uint8_t contrast)
|
|
{
|
|
setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07);
|
|
}
|
|
|
|
/* Next 3 functions are 310/325 series only */
|
|
|
|
static void set_saturation(char saturation)
|
|
{
|
|
uint8_t temp = 0;
|
|
|
|
if (saturation < 0) {
|
|
temp |= 0x88;
|
|
saturation = -saturation;
|
|
}
|
|
temp |= (saturation & 0x07);
|
|
temp |= ((saturation & 0x07) << 4);
|
|
|
|
setvideoreg(Index_VI_Saturation, temp);
|
|
}
|
|
|
|
static void set_hue(uint8_t hue)
|
|
{
|
|
setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue);
|
|
}
|
|
|
|
#if 0
|
|
/* JCP: not used (I don't think it's correct anyway) */
|
|
static void set_alpha(uint8_t alpha)
|
|
{
|
|
uint8_t data;
|
|
|
|
data = getvideoreg(Index_VI_Key_Overlay_OP);
|
|
data &= 0x0F;
|
|
setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4));
|
|
}
|
|
#endif
|