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c6d4298b7b
S3 registers header file. git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@26129 b3059339-0415-0410-9bf9-f77b7e298cf2
215 lines
7.7 KiB
C
215 lines
7.7 KiB
C
#ifndef MPLAYER_SAVAGE_REGS_H
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#define MPLAYER_SAVAGE_REGS_H
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#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
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#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
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#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
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#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
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/*
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* Chip tags. These are used to group the adapters into
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* related families.
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*/
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enum S3CHIPTAGS {
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S3_UNKNOWN = 0,
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S3_TRIO64V,
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S3_VIRGE,
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S3_SAVAGE3D,
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S3_SAVAGE_MX,
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S3_SAVAGE4,
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S3_PROSAVAGE,
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S3_SUPERSAVAGE,
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S3_SAVAGE2000,
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S3_LAST
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};
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#define BIOS_BSIZE 1024
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#define BIOS_BASE 0xc0000
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#define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */
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#define S3_NEWMMIO_REGSIZE 0x0010000 /* 64KB */
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#define S3_NEWMMIO_REGSIZE_SAVAGE 0x0080000 /* 512KB */
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#define BASE_FREQ 14.31818
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/*
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* There are two different streams engines used in the S3 line.
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* The old engine is in the Trio64, Virge,
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* Savage3D, Savage4, SavagePro, and SavageTwister.
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* The new engine is in the Savage2000, SavageMX,
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* SavageIX, and SuperSavage.
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*/
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/* Old engine registers */
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#define PSTREAM_CONTROL_REG 0x8180
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#define COL_CHROMA_KEY_CONTROL_REG 0x8184
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#define SSTREAM_CONTROL_REG 0x8190
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#define CHROMA_KEY_UPPER_BOUND_REG 0x8194
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#define SSTREAM_STRETCH_REG 0x8198
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#define COLOR_ADJUSTMENT_REG 0x819C
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#define BLEND_CONTROL_REG 0x81A0
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#define PSTREAM_FBADDR0_REG 0x81C0
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#define PSTREAM_FBADDR1_REG 0x81C4
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#define PSTREAM_STRIDE_REG 0x81C8
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#define DOUBLE_BUFFER_REG 0x81CC
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#define SSTREAM_FBADDR0_REG 0x81D0
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#define SSTREAM_FBADDR1_REG 0x81D4
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#define SSTREAM_STRIDE_REG 0x81D8
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#define OPAQUE_OVERLAY_CONTROL_REG 0x81DC
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#define K1_VSCALE_REG 0x81E0
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#define SSTREAM_VSCALE_REG 0x81E0
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#define K2_VSCALE_REG 0x81E4
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#define SSTREAM_VINITIAL_REG 0x81E4
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#define DDA_VERT_REG 0x81E8
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#define SSTREAM_LINES_REG 0x81E8
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#define STREAMS_FIFO_REG 0x81EC
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#define PSTREAM_WINDOW_START_REG 0x81F0
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#define PSTREAM_WINDOW_SIZE_REG 0x81F4
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#define SSTREAM_WINDOW_START_REG 0x81F8
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#define SSTREAM_WINDOW_SIZE_REG 0x81FC
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#define FIFO_CONTROL 0x8200
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#define PSTREAM_FBSIZE_REG 0x8300
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#define SSTREAM_FBSIZE_REG 0x8304
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#define SSTREAM_FBADDR2_REG 0x8308
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/* New engine registers */
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#define PRI_STREAM_FBUF_ADDR0 0x81c0
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#define PRI_STREAM_FBUF_ADDR1 0x81c4
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#define PRI_STREAM_STRIDE 0x81c8
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#define PRI_STREAM_BUFFERSIZE 0x8214
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#define SEC_STREAM_CKEY_LOW 0x8184
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#define SEC_STREAM_CKEY_UPPER 0x8194
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#define BLEND_CONTROL 0x8190
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#define SEC_STREAM_COLOR_CONVERT1 0x8198
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#define SEC_STREAM_COLOR_CONVERT2 0x819c
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#define SEC_STREAM_COLOR_CONVERT3 0x81e4
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#define SEC_STREAM_HSCALING 0x81a0
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#define SEC_STREAM_BUFFERSIZE 0x81a8
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#define SEC_STREAM_HSCALE_NORMALIZE 0x81ac
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#define SEC_STREAM_VSCALING 0x81e8
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#define SEC_STREAM_FBUF_ADDR0 0x81d0
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#define SEC_STREAM_FBUF_ADDR1 0x81d4
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#define SEC_STREAM_FBUF_ADDR2 0x81ec
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#define SEC_STREAM_STRIDE 0x81d8
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#define SEC_STREAM_WINDOW_START 0x81f8
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#define SEC_STREAM_WINDOW_SZ 0x81fc
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#define SEC_STREAM_TILE_OFF 0x821c
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#define SEC_STREAM_OPAQUE_OVERLAY 0x81dc
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/* Savage 2000 registers */
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#define SEC_STREAM_COLOR_CONVERT0_2000 0x8198
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#define SEC_STREAM_COLOR_CONVERT1_2000 0x819c
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#define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0
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#define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4
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/* Virge+ registers */
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#define FIFO_CONTROL_REG 0x8200
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#define MIU_CONTROL_REG 0x8204
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#define STREAMS_TIMEOUT_REG 0x8208
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#define MISC_TIMEOUT_REG 0x820c
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/* VGA stuff */
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#define vgaCRIndex 0x3d4
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#define vgaCRReg 0x3d5
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/* CRT Control registers */
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#define EXT_MEM_CTRL1 0x53
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#define LIN_ADDR_CTRL 0x58
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#define EXT_MISC_CTRL2 0x67
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/* Old engine constants */
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#define ENABLE_NEWMMIO 0x08
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#define ENABLE_LFB 0x10
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#define ENABLE_STREAMS_OLD 0x0c
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#define NO_STREAMS_OLD 0xf3
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/* New engine constants */
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#define ENABLE_STREAM1 0x04
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#define NO_STREAMS 0xF9
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#define VerticalRetraceWait() \
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do { \
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VGAIN8(0x3d4); \
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VGAOUT8(0x3d4, 0x17); \
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if (VGAIN8(0x3d5) & 0x80) { \
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int i = 0x10000; \
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while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \
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i = 0x10000; \
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while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \
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} \
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} while (0)
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/* Scaling operations */
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#define HSCALING_Shift 0
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#define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift)
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#define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) << HSCALING_Shift) & HSCALING_Mask)
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#define VSCALING_Shift 0
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#define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift)
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#define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) << VSCALING_Shift) & VSCALING_Mask)
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/* Scaling factors */
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#define HDM_SHIFT 16
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#define HDSCALE_4 (2 << HDM_SHIFT)
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#define HDSCALE_8 (3 << HDM_SHIFT)
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#define HDSCALE_16 (4 << HDM_SHIFT)
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#define HDSCALE_32 (5 << HDM_SHIFT)
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#define HDSCALE_64 (6 << HDM_SHIFT)
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/* Window parameters */
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#define OS_XY(x,y) (((x+1)<<16)|(y+1))
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#define OS_WH(x,y) (((x-1)<<16)|(y))
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/* PCI stuff */
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/* PCI-Memory IO access macros. */
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#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val))
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#define VID_RD08(p,i) (((uint8_t *)(p))[(i)])
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#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val))
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#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4])
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#ifndef USE_RMW_CYCLES
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/* Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. */
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#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
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#undef VID_WR08
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#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
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#undef VID_RD08
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#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
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#undef VID_WR16
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#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); })
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#undef VID_RD16
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#define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; })
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#undef VID_WR32
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#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
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#undef VID_RD32
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#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
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#endif /* USE_RMW_CYCLES */
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#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
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#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
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#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
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#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr)
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#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr)
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#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr)
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#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val)
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#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val)
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#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val)
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#define INREG(addr) VID_RD32(info->control_base, addr)
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#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val)
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#define INREG8(addr) VID_RD08(info->control_base, addr)
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#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val)
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#define INREG16(addr) VID_RD16(info->control_base, addr)
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#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val)
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#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))
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#endif /* MPLAYER_S3_REGS_H */
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