mirror of
https://github.com/mpv-player/mpv
synced 2024-12-25 16:33:02 +00:00
69e3e06a1a
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@32421 b3059339-0415-0410-9bf9-f77b7e298cf2
540 lines
16 KiB
C
540 lines
16 KiB
C
/*
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* This file is part of MPlayer.
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*
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* MPlayer is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* MPlayer is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with MPlayer; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "config.h"
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#include "cpudetect.h"
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#include "mp_msg.h"
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CpuCaps gCpuCaps;
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#include <stdlib.h>
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#if ARCH_X86
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#include <stdio.h>
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#include <string.h>
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#if defined (__NetBSD__) || defined(__OpenBSD__)
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <machine/cpu.h>
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
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#include <sys/types.h>
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#include <sys/sysctl.h>
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#elif defined(__linux__)
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#include <signal.h>
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#elif defined(__MINGW32__) || defined(__CYGWIN__)
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#include <windows.h>
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#elif defined(__OS2__)
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#define INCL_DOS
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#include <os2.h>
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#elif defined(__AMIGAOS4__)
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#include <proto/exec.h>
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#endif
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/* Thanks to the FreeBSD project for some of this cpuid code, and
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* help understanding how to use it. Thanks to the Mesa
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* team for SSE support detection and more cpu detect code.
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*/
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/* I believe this code works. However, it has only been used on a PII and PIII */
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#if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
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static void sigill_handler_sse( int signal, struct sigcontext sc )
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{
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mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
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/* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
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* instructions are 3 bytes long. We must increment the instruction
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* pointer manually to avoid repeated execution of the offending
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* instruction.
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*
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* If the SIGILL is caused by a divide-by-zero when unmasked
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* exceptions aren't supported, the SIMD FPU status and control
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* word will be restored at the end of the test, so we don't need
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* to worry about doing it here. Besides, we may not be able to...
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*/
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sc.eip += 3;
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gCpuCaps.hasSSE=0;
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}
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#endif /* __linux__ && _POSIX_SOURCE */
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#if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
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LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
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{
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if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
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mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
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ep->ContextRecord->Eip +=3;
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gCpuCaps.hasSSE=0;
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return EXCEPTION_CONTINUE_EXECUTION;
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}
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return EXCEPTION_CONTINUE_SEARCH;
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}
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#endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
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#ifdef __OS2__
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ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1,
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PEXCEPTIONREGISTRATIONRECORD p2,
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PCONTEXTRECORD p3,
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PVOID p4)
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{
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if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
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mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
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p3->ctx_RegEip += 3;
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gCpuCaps.hasSSE = 0;
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return XCPT_CONTINUE_EXECUTION;
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}
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return XCPT_CONTINUE_SEARCH;
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}
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#endif
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/* If we're running on a processor that can do SSE, let's see if we
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* are allowed to or not. This will catch 2.4.0 or later kernels that
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* haven't been configured for a Pentium III but are running on one,
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* and RedHat patched 2.2 kernels that have broken exception handling
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* support for user space apps that do SSE.
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*/
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#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
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#define SSE_SYSCTL_NAME "hw.instruction_sse"
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#elif defined(__APPLE__)
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#define SSE_SYSCTL_NAME "hw.optional.sse"
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#endif
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static void check_os_katmai_support( void )
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{
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#if ARCH_X86_64
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gCpuCaps.hasSSE=1;
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gCpuCaps.hasSSE2=1;
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
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int has_sse=0, ret;
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size_t len=sizeof(has_sse);
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ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
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if (ret || !has_sse)
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gCpuCaps.hasSSE=0;
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#elif defined(__NetBSD__) || defined (__OpenBSD__)
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#if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
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int has_sse, has_sse2, ret, mib[2];
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size_t varlen;
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mib[0] = CTL_MACHDEP;
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mib[1] = CPU_SSE;
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varlen = sizeof(has_sse);
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
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ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
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gCpuCaps.hasSSE = ret >= 0 && has_sse;
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mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
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mib[1] = CPU_SSE2;
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varlen = sizeof(has_sse2);
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
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ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
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gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
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mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
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#else
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gCpuCaps.hasSSE = 0;
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mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
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#endif
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#elif defined(__MINGW32__) || defined(__CYGWIN__)
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LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
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if ( gCpuCaps.hasSSE ) {
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
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exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
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__asm__ volatile ("xorps %xmm0, %xmm0");
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SetUnhandledExceptionFilter(exc_fil);
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mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
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}
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#elif defined(__OS2__)
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EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
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if ( gCpuCaps.hasSSE ) {
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
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DosSetExceptionHandler( &RegRec );
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__asm__ volatile ("xorps %xmm0, %xmm0");
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DosUnsetExceptionHandler( &RegRec );
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mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
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}
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#elif defined(__linux__)
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#if defined(_POSIX_SOURCE)
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struct sigaction saved_sigill;
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/* Save the original signal handlers.
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*/
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sigaction( SIGILL, NULL, &saved_sigill );
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signal( SIGILL, (void (*)(int))sigill_handler_sse );
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/* Emulate test for OSFXSR in CR4. The OS will set this bit if it
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* supports the extended FPU save and restore required for SSE. If
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* we execute an SSE instruction on a PIII and get a SIGILL, the OS
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* doesn't support Streaming SIMD Exceptions, even if the processor
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* does.
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*/
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if ( gCpuCaps.hasSSE ) {
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
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// __asm__ volatile ("xorps %%xmm0, %%xmm0");
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__asm__ volatile ("xorps %xmm0, %xmm0");
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mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
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}
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/* Restore the original signal handlers.
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*/
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sigaction( SIGILL, &saved_sigill, NULL );
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/* If we've gotten to here and the XMM CPUID bit is still set, we're
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* safe to go ahead and hook out the SSE code throughout Mesa.
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*/
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mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
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#else
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/* We can't use POSIX signal handling to test the availability of
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* SSE, so we disable it by default.
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*/
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mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
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gCpuCaps.hasSSE=0;
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#endif /* _POSIX_SOURCE */
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#else
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/* Do nothing on other platforms for now.
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*/
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mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
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gCpuCaps.hasSSE=0;
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#endif /* __linux__ */
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}
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// return TRUE if cpuid supported
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static int has_cpuid(void)
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{
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// code from libavcodec:
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#if ARCH_X86_64
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return 1;
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#else
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long a, c;
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__asm__ volatile (
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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"pushfl\n\t"
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"pop %0\n\t"
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"mov %0, %1\n\t"
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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"xor $0x200000, %0\n\t"
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"push %0\n\t"
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"popfl\n\t"
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/* ... Get the (hopefully modified) EFLAGS */
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"pushfl\n\t"
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"pop %0\n\t"
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: "=a" (a), "=c" (c)
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:
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: "cc"
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);
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return a != c;
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#endif
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}
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void
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do_cpuid(unsigned int ax, unsigned int *p)
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{
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// code from libavcodec:
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__asm__ volatile
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("mov %%"REG_b", %%"REG_S"\n\t"
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"cpuid\n\t"
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"xchg %%"REG_b", %%"REG_S
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: "=a" (p[0]), "=S" (p[1]),
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"=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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}
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void GetCpuCaps( CpuCaps *caps)
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{
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unsigned int regs[4];
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unsigned int regs2[4];
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memset(caps, 0, sizeof(*caps));
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caps->isX86=1;
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caps->cl_size=32; /* default */
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if (!has_cpuid()) {
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mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
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return;
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}
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do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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(char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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if (regs[0]>=0x00000001)
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{
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char *tmpstr, *ptmpstr;
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unsigned cl_size;
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do_cpuid(0x00000001, regs2);
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caps->cpuType=(regs2[0] >> 8)&0xf;
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caps->cpuModel=(regs2[0] >> 4)&0xf;
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// see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
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// System Instructions, Table 3-2: Effective family computation, page 120.
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if(caps->cpuType==0xf){
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// use extended family (P4, IA64, K8)
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caps->cpuType=0xf+((regs2[0]>>20)&255);
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}
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if(caps->cpuType==0xf || caps->cpuType==6)
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caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
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caps->cpuStepping=regs2[0] & 0xf;
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// general feature flags:
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caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010
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caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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caps->hasSSE3 = (regs2[2] & 1); // 0x0000001
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caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200
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caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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cl_size = ((regs2[1] >> 8) & 0xFF)*8;
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if(cl_size) caps->cl_size = cl_size;
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ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
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while(*ptmpstr == ' ') // strip leading spaces
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ptmpstr++;
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mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
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free(tmpstr);
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mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
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caps->cpuType, caps->cpuModel, caps->cpuStepping);
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}
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do_cpuid(0x80000000, regs);
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if (regs[0]>=0x80000001) {
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mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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do_cpuid(0x80000001, regs2);
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caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040
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}
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if(regs[0]>=0x80000006)
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{
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do_cpuid(0x80000006, regs2);
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mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
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caps->cl_size = regs2[2] & 0xFF;
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}
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mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
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#if 0
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mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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gCpuCaps.hasMMX,
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gCpuCaps.hasMMX2,
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gCpuCaps.hasSSE,
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gCpuCaps.hasSSE2,
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gCpuCaps.has3DNow,
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gCpuCaps.has3DNowExt);
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#endif
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/* FIXME: Does SSE2 need more OS support, too? */
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if (caps->hasSSE)
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check_os_katmai_support();
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if (!caps->hasSSE)
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caps->hasSSE2 = 0;
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// caps->has3DNow=1;
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// caps->hasMMX2 = 0;
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// caps->hasMMX = 0;
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#if !CONFIG_RUNTIME_CPUDETECT
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#if !HAVE_MMX
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if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
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caps->hasMMX=0;
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#endif
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#if !HAVE_MMX2
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if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
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caps->hasMMX2=0;
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#endif
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#if !HAVE_SSE
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if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
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caps->hasSSE=0;
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#endif
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#if !HAVE_SSE2
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if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
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caps->hasSSE2=0;
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#endif
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#if !HAVE_AMD3DNOW
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if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
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caps->has3DNow=0;
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#endif
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#if !HAVE_AMD3DNOWEXT
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if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
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caps->has3DNowExt=0;
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#endif
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#endif // CONFIG_RUNTIME_CPUDETECT
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}
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char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
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char vendor[13];
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char *retname;
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int i;
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if (NULL==(retname=malloc(256))) {
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mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
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exit(1);
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}
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retname[0] = '\0';
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sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
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do_cpuid(0x80000000,regs);
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if (regs[0] >= 0x80000004)
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{
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// CPU has built-in namestring
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for (i = 0x80000002; i <= 0x80000004; i++)
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{
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do_cpuid(i, regs);
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strncat(retname, (char*)regs, 16);
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}
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}
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return retname;
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}
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#else /* ARCH_X86 */
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#ifdef __APPLE__
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#include <sys/sysctl.h>
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#elif defined(__AMIGAOS4__)
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/* nothing */
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#else
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#include <signal.h>
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#include <setjmp.h>
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static sigjmp_buf jmpbuf;
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static volatile sig_atomic_t canjump = 0;
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static void sigill_handler (int sig)
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{
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|
if (!canjump) {
|
|
signal (sig, SIG_DFL);
|
|
raise (sig);
|
|
}
|
|
|
|
canjump = 0;
|
|
siglongjmp (jmpbuf, 1);
|
|
}
|
|
#endif /* __APPLE__ */
|
|
|
|
void GetCpuCaps( CpuCaps *caps)
|
|
{
|
|
caps->cpuType=0;
|
|
caps->cpuModel=0;
|
|
caps->cpuStepping=0;
|
|
caps->hasMMX=0;
|
|
caps->hasMMX2=0;
|
|
caps->has3DNow=0;
|
|
caps->has3DNowExt=0;
|
|
caps->hasSSE=0;
|
|
caps->hasSSE2=0;
|
|
caps->hasSSE3=0;
|
|
caps->hasSSSE3=0;
|
|
caps->hasSSE4a=0;
|
|
caps->isX86=0;
|
|
caps->hasAltiVec = 0;
|
|
#if HAVE_ALTIVEC
|
|
#ifdef __APPLE__
|
|
/*
|
|
rip-off from ffmpeg altivec detection code.
|
|
this code also appears on Apple's AltiVec pages.
|
|
*/
|
|
{
|
|
int sels[2] = {CTL_HW, HW_VECTORUNIT};
|
|
int has_vu = 0;
|
|
size_t len = sizeof(has_vu);
|
|
int err;
|
|
|
|
err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
|
|
|
|
if (err == 0)
|
|
if (has_vu != 0)
|
|
caps->hasAltiVec = 1;
|
|
}
|
|
#elif defined(__AMIGAOS4__)
|
|
ULONG result = 0;
|
|
|
|
GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
|
|
if (result == VECTORTYPE_ALTIVEC)
|
|
caps->hasAltiVec = 1;
|
|
#else
|
|
/* no Darwin, do it the brute-force way */
|
|
/* this is borrowed from the libmpeg2 library */
|
|
{
|
|
signal (SIGILL, sigill_handler);
|
|
if (sigsetjmp (jmpbuf, 1)) {
|
|
signal (SIGILL, SIG_DFL);
|
|
} else {
|
|
canjump = 1;
|
|
|
|
__asm__ volatile ("mtspr 256, %0\n\t"
|
|
"vand %%v0, %%v0, %%v0"
|
|
:
|
|
: "r" (-1));
|
|
|
|
signal (SIGILL, SIG_DFL);
|
|
caps->hasAltiVec = 1;
|
|
}
|
|
}
|
|
#endif /* __APPLE__ */
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
|
|
#endif /* HAVE_ALTIVEC */
|
|
|
|
if (ARCH_IA64)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
|
|
|
|
if (ARCH_SPARC)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
|
|
|
|
if (ARCH_ARM)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
|
|
|
|
if (ARCH_PPC)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
|
|
|
|
if (ARCH_ALPHA)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
|
|
|
|
if (ARCH_MIPS)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
|
|
|
|
if (ARCH_PA_RISC)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
|
|
|
|
if (ARCH_S390)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
|
|
|
|
if (ARCH_S390X)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
|
|
|
|
if (ARCH_VAX)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
|
|
|
|
if (ARCH_XTENSA)
|
|
mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
|
|
}
|
|
#endif /* !ARCH_X86 */
|