mirror of
https://github.com/mpv-player/mpv
synced 2024-12-25 16:33:02 +00:00
bbcccf2d19
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@27604 b3059339-0415-0410-9bf9-f77b7e298cf2
324 lines
7.7 KiB
ArmAsm
324 lines
7.7 KiB
ArmAsm
@ motion_comp_arm_s.S
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@ Copyright (C) 2004 AGAWA Koji <i (AT) atty (DOT) jp>
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@
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@ This file is part of mpeg2dec, a free MPEG-2 video stream decoder.
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@ See http://libmpeg2.sourceforge.net/ for updates.
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@
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@ mpeg2dec is free software; you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation; either version 2 of the License, or
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@ (at your option) any later version.
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@
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@ mpeg2dec is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with mpeg2dec; if not, write to the Free Software
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@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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.text
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@ ----------------------------------------------------------------
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.align
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.global MC_put_o_16_arm
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MC_put_o_16_arm:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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pld [r1]
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stmfd sp!, {r4-r11, lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_o_16_arm_align_jt
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add r5, r5, r4, lsl #2
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ldr pc, [r5]
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MC_put_o_16_arm_align0:
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ldmia r1, {r4-r7}
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add r1, r1, r2
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pld [r1]
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stmia r0, {r4-r7}
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_o_16_arm_align0
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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.macro PROC shift
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ldmia r1, {r4-r8}
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add r1, r1, r2
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mov r9, r4, lsr #(\shift)
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pld [r1]
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mov r10, r5, lsr #(\shift)
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orr r9, r9, r5, lsl #(32-\shift)
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mov r11, r6, lsr #(\shift)
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orr r10, r10, r6, lsl #(32-\shift)
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mov r12, r7, lsr #(\shift)
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orr r11, r11, r7, lsl #(32-\shift)
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orr r12, r12, r8, lsl #(32-\shift)
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stmia r0, {r9-r12}
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subs r3, r3, #1
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add r0, r0, r2
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.endm
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MC_put_o_16_arm_align1:
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and r1, r1, #0xFFFFFFFC
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1: PROC(8)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_arm_align2:
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and r1, r1, #0xFFFFFFFC
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1: PROC(16)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_arm_align3:
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and r1, r1, #0xFFFFFFFC
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1: PROC(24)
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bne 1b
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ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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MC_put_o_16_arm_align_jt:
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.word MC_put_o_16_arm_align0
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.word MC_put_o_16_arm_align1
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.word MC_put_o_16_arm_align2
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.word MC_put_o_16_arm_align3
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@ ----------------------------------------------------------------
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.align
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.global MC_put_o_8_arm
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MC_put_o_8_arm:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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pld [r1]
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stmfd sp!, {r4-r10, lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_o_8_arm_align_jt
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add r5, r5, r4, lsl #2
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ldr pc, [r5]
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MC_put_o_8_arm_align0:
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ldmia r1, {r4-r5}
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add r1, r1, r2
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pld [r1]
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stmia r0, {r4-r5}
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add r0, r0, r2
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subs r3, r3, #1
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bne MC_put_o_8_arm_align0
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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.macro PROC8 shift
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ldmia r1, {r4-r6}
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add r1, r1, r2
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mov r9, r4, lsr #(\shift)
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pld [r1]
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mov r10, r5, lsr #(\shift)
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orr r9, r9, r5, lsl #(32-\shift)
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orr r10, r10, r6, lsl #(32-\shift)
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stmia r0, {r9-r10}
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subs r3, r3, #1
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add r0, r0, r2
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.endm
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MC_put_o_8_arm_align1:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(8)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_arm_align2:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(16)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_arm_align3:
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and r1, r1, #0xFFFFFFFC
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1: PROC8(24)
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bne 1b
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ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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MC_put_o_8_arm_align_jt:
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.word MC_put_o_8_arm_align0
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.word MC_put_o_8_arm_align1
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.word MC_put_o_8_arm_align2
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.word MC_put_o_8_arm_align3
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@ ----------------------------------------------------------------
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.macro AVG_PW rW1, rW2
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mov \rW2, \rW2, lsl #24
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orr \rW2, \rW2, \rW1, lsr #8
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eor r9, \rW1, \rW2
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and \rW2, \rW1, \rW2
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and r10, r9, r12
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add \rW2, \rW2, r10, lsr #1
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and r10, r9, r11
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add \rW2, \rW2, r10
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.endm
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.align
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.global MC_put_x_16_arm
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MC_put_x_16_arm:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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pld [r1]
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stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_x_16_arm_align_jt
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ldr r11, [r5]
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mvn r12, r11
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add r5, r5, r4, lsl #2
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ldr pc, [r5, #4]
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.macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
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mov \R0, \R0, lsr #(\shift)
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orr \R0, \R0, \R1, lsl #(32 - \shift)
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mov \R1, \R1, lsr #(\shift)
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orr \R1, \R1, \R2, lsl #(32 - \shift)
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mov \R2, \R2, lsr #(\shift)
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orr \R2, \R2, \R3, lsl #(32 - \shift)
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mov \R3, \R3, lsr #(\shift)
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orr \R3, \R3, \R4, lsl #(32 - \shift)
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mov \R4, \R4, lsr #(\shift)
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@ and \R4, \R4, #0xFF
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.endm
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MC_put_x_16_arm_align0:
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ldmia r1, {r4-r8}
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add r1, r1, r2
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pld [r1]
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AVG_PW r7, r8
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AVG_PW r6, r7
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_16_arm_align0
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_16_arm_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_QW 8, r4, r5, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_16_arm_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_QW 16, r4, r5, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_16_arm_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r8}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_QW 24, r4, r5, r6, r7, r8
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AVG_PW r7, r8
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AVG_PW r6, r7
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r8}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_16_arm_align_jt:
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.word 0x01010101
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.word MC_put_x_16_arm_align0
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.word MC_put_x_16_arm_align1
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.word MC_put_x_16_arm_align2
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.word MC_put_x_16_arm_align3
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@ ----------------------------------------------------------------
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.align
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.global MC_put_x_8_arm
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MC_put_x_8_arm:
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@@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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pld [r1]
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stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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and r4, r1, #3
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adr r5, MC_put_x_8_arm_align_jt
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ldr r11, [r5]
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mvn r12, r11
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add r5, r5, r4, lsl #2
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ldr pc, [r5, #4]
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.macro ADJ_ALIGN_DW shift, R0, R1, R2
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mov \R0, \R0, lsr #(\shift)
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orr \R0, \R0, \R1, lsl #(32 - \shift)
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mov \R1, \R1, lsr #(\shift)
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orr \R1, \R1, \R2, lsl #(32 - \shift)
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mov \R2, \R2, lsr #(\shift)
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@ and \R4, \R4, #0xFF
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.endm
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MC_put_x_8_arm_align0:
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ldmia r1, {r4-r6}
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add r1, r1, r2
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pld [r1]
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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subs r3, r3, #1
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add r0, r0, r2
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bne MC_put_x_8_arm_align0
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_8_arm_align1:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_DW 8, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_8_arm_align2:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_DW 16, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_8_arm_align3:
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and r1, r1, #0xFFFFFFFC
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1: ldmia r1, {r4-r6}
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add r1, r1, r2
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pld [r1]
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ADJ_ALIGN_DW 24, r4, r5, r6
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AVG_PW r5, r6
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AVG_PW r4, r5
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stmia r0, {r5-r6}
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subs r3, r3, #1
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add r0, r0, r2
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bne 1b
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ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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MC_put_x_8_arm_align_jt:
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.word 0x01010101
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.word MC_put_x_8_arm_align0
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.word MC_put_x_8_arm_align1
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.word MC_put_x_8_arm_align2
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.word MC_put_x_8_arm_align3
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