mirror of
https://github.com/mpv-player/mpv
synced 2024-12-25 16:33:02 +00:00
7ef7eddfc5
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4830 b3059339-0415-0410-9bf9-f77b7e298cf2
393 lines
11 KiB
C
393 lines
11 KiB
C
#include "config.h"
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#include "cpudetect.h"
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CpuCaps gCpuCaps;
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#ifdef HAVE_MALLOC_H
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#include <malloc.h>
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#endif
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#include <stdlib.h>
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#ifdef ARCH_X86
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#include <stdio.h>
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#ifdef __FreeBSD__
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#include <sys/types.h>
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#include <sys/sysctl.h>
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#endif
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#ifdef __linux__
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#include <signal.h>
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#endif
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//#define X86_FXSR_MAGIC
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/* Thanks to the FreeBSD project for some of this cpuid code, and
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* help understanding how to use it. Thanks to the Mesa
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* team for SSE support detection and more cpu detect code.
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*/
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/* I believe this code works. However, it has only been used on a PII and PIII */
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static void check_os_katmai_support( void );
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#if 1
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// return TRUE if cpuid supported
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static int has_cpuid()
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{
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int a, c;
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// code from libavcodec:
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__asm__ __volatile__ (
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/* See if CPUID instruction is supported ... */
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/* ... Get copies of EFLAGS into eax and ecx */
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"pushf\n\t"
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"popl %0\n\t"
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"movl %0, %1\n\t"
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/* ... Toggle the ID bit in one copy and store */
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/* to the EFLAGS reg */
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"xorl $0x200000, %0\n\t"
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"push %0\n\t"
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"popf\n\t"
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/* ... Get the (hopefully modified) EFLAGS */
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"pushf\n\t"
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"popl %0\n\t"
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: "=a" (a), "=c" (c)
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:
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: "cc"
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);
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return (a!=c);
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}
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#endif
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static void
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do_cpuid(unsigned int ax, unsigned int *p)
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{
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#if 0
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__asm __volatile(
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"cpuid;"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax)
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);
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#else
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// code from libavcodec:
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__asm __volatile
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("movl %%ebx, %%esi\n\t"
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"cpuid\n\t"
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"xchgl %%ebx, %%esi"
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: "=a" (p[0]), "=S" (p[1]),
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"=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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#endif
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}
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void GetCpuCaps( CpuCaps *caps)
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{
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unsigned int regs[4];
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unsigned int regs2[4];
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caps->isX86=1;
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memset(caps, 0, sizeof(*caps));
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if (!has_cpuid()) {
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printf("CPUID not supported!???\n");
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return;
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}
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do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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printf("CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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(char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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if (regs[0]>=0x00000001)
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{
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char *tmpstr;
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do_cpuid(0x00000001, regs2);
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tmpstr=GetCpuFriendlyName(regs, regs2);
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printf("CPU: %s ",tmpstr);
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free(tmpstr);
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caps->cpuType=(regs2[0] >> 8)&0xf;
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if(caps->cpuType==0xf){
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// use extended family (P4, IA64)
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caps->cpuType=8+((regs2[0]>>20)&255);
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}
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caps->cpuStepping=regs2[0] & 0xf;
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printf("(Type: %d, Stepping: %d)\n",
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caps->cpuType, caps->cpuStepping);
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// general feature flags:
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caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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}
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do_cpuid(0x80000000, regs);
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if (regs[0]>=0x80000001) {
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printf("extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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do_cpuid(0x80000001, regs2);
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caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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}
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#if 0
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printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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gCpuCaps.hasMMX,
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gCpuCaps.hasMMX2,
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gCpuCaps.hasSSE,
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gCpuCaps.hasSSE2,
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gCpuCaps.has3DNow,
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gCpuCaps.has3DNowExt );
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#endif
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/* FIXME: Does SSE2 need more OS support, too? */
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#if defined(__linux__) || defined(__FreeBSD__)
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if (caps->hasSSE)
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check_os_katmai_support();
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if (!caps->hasSSE)
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caps->hasSSE2 = 0;
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#else
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caps->hasSSE=0;
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caps->hasSSE2 = 0;
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#endif
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// caps->has3DNow=1;
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// caps->hasMMX2 = 0;
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// caps->hasMMX = 0;
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#ifndef HAVE_MMX
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if(caps->hasMMX) printf("MMX supported but disabled\n");
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caps->hasMMX=0;
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#endif
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#ifndef HAVE_MMX2
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if(caps->hasMMX2) printf("MMX2 supported but disabled\n");
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caps->hasMMX2=0;
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#endif
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#ifndef HAVE_SSE
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if(caps->hasSSE) printf("SSE supported but disabled\n");
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caps->hasSSE=0;
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#endif
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#ifndef HAVE_SSE2
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if(caps->hasSSE2) printf("SSE2 supported but disabled\n");
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caps->hasSSE2=0;
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#endif
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#ifndef HAVE_3DNOW
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if(caps->has3DNow) printf("3DNow supported but disabled\n");
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caps->has3DNow=0;
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#endif
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#ifndef HAVE_3DNOWEX
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if(caps->has3DNowExt) printf("3DNowExt supported but disabled\n");
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caps->has3DNowExt=0;
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#endif
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}
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#define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
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#define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
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#define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
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#define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
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#define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
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#define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
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char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
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#include "cputable.h" /* get cpuname and cpuvendors */
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char vendor[17];
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char *retname;
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int i;
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if (NULL==(retname=(char*)malloc(256))) {
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printf("Error: GetCpuFriendlyName() not enough memory\n");
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exit(1);
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}
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sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
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for(i=0; i<MAX_VENDORS; i++){
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if(!strcmp(cpuvendors[i].string,vendor)){
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if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
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snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
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} else {
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snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
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printf("unknown %s CPU:\n",cpuvendors[i].name);
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printf("Vendor: %s\n",cpuvendors[i].string);
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printf("Type: %d\n",CPUID_TYPE);
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printf("Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
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printf("Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
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printf("Stepping: %d\n",CPUID_STEPPING);
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printf("Please send the above info along with the exact CPU name"
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"to the MPlayer-Developers, so we can add it to the list!\n");
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}
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}
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}
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//printf("Detected CPU: %s\n", retname);
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return retname;
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}
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#undef CPUID_EXTFAMILY
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#undef CPUID_EXTMODEL
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#undef CPUID_TYPE
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#undef CPUID_FAMILY
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#undef CPUID_MODEL
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#undef CPUID_STEPPING
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#if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
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static void sigill_handler_sse( int signal, struct sigcontext sc )
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{
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printf( "SIGILL, " );
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/* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
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* instructions are 3 bytes long. We must increment the instruction
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* pointer manually to avoid repeated execution of the offending
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* instruction.
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*
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* If the SIGILL is caused by a divide-by-zero when unmasked
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* exceptions aren't supported, the SIMD FPU status and control
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* word will be restored at the end of the test, so we don't need
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* to worry about doing it here. Besides, we may not be able to...
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*/
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sc.eip += 3;
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gCpuCaps.hasSSE=0;
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}
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static void sigfpe_handler_sse( int signal, struct sigcontext sc )
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{
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printf( "SIGFPE, " );
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if ( sc.fpstate->magic != 0xffff ) {
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/* Our signal context has the extended FPU state, so reset the
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* divide-by-zero exception mask and clear the divide-by-zero
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* exception bit.
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*/
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sc.fpstate->mxcsr |= 0x00000200;
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sc.fpstate->mxcsr &= 0xfffffffb;
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} else {
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/* If we ever get here, we're completely hosed.
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*/
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printf( "\n\n" );
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printf( "SSE enabling test failed badly!" );
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}
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}
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#endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
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/* If we're running on a processor that can do SSE, let's see if we
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* are allowed to or not. This will catch 2.4.0 or later kernels that
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* haven't been configured for a Pentium III but are running on one,
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* and RedHat patched 2.2 kernels that have broken exception handling
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* support for user space apps that do SSE.
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*/
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static void check_os_katmai_support( void )
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{
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#if defined(__FreeBSD__)
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int has_sse=0, ret;
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size_t len=sizeof(has_sse);
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ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
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if (ret || !has_sse)
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gCpuCaps.hasSSE=0;
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#elif defined(__linux__)
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#if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
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struct sigaction saved_sigill;
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struct sigaction saved_sigfpe;
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/* Save the original signal handlers.
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*/
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sigaction( SIGILL, NULL, &saved_sigill );
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sigaction( SIGFPE, NULL, &saved_sigfpe );
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signal( SIGILL, (void (*)(int))sigill_handler_sse );
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signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
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/* Emulate test for OSFXSR in CR4. The OS will set this bit if it
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* supports the extended FPU save and restore required for SSE. If
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* we execute an SSE instruction on a PIII and get a SIGILL, the OS
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* doesn't support Streaming SIMD Exceptions, even if the processor
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* does.
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*/
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if ( gCpuCaps.hasSSE ) {
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printf( "Testing OS support for SSE... " );
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// __asm __volatile ("xorps %%xmm0, %%xmm0");
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__asm __volatile ("xorps %xmm0, %xmm0");
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if ( gCpuCaps.hasSSE ) {
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printf( "yes.\n" );
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} else {
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printf( "no!\n" );
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}
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}
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/* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
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* it supports unmasked SIMD FPU exceptions. If we unmask the
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* exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
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* doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
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* as expected, we're okay but we need to clean up after it.
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*
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* Are we being too stringent in our requirement that the OS support
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* unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
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* setting CR4.OSFXSR but don't support unmasked exceptions. Win98
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* doesn't even support them. We at least know the user-space SSE
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* support is good in kernels that do support unmasked exceptions,
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* and therefore to be safe I'm going to leave this test in here.
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*/
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if ( gCpuCaps.hasSSE ) {
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printf( "Testing OS support for SSE unmasked exceptions... " );
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// test_os_katmai_exception_support();
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if ( gCpuCaps.hasSSE ) {
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printf( "yes.\n" );
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} else {
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printf( "no!\n" );
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}
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}
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/* Restore the original signal handlers.
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*/
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sigaction( SIGILL, &saved_sigill, NULL );
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sigaction( SIGFPE, &saved_sigfpe, NULL );
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/* If we've gotten to here and the XMM CPUID bit is still set, we're
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* safe to go ahead and hook out the SSE code throughout Mesa.
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*/
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if ( gCpuCaps.hasSSE ) {
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printf( "Tests of OS support for SSE passed.\n" );
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} else {
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printf( "Tests of OS support for SSE failed!\n" );
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}
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#else
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/* We can't use POSIX signal handling to test the availability of
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* SSE, so we disable it by default.
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*/
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printf( "Cannot test OS support for SSE, disabling to be safe.\n" );
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gCpuCaps.hasSSE=0;
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#endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
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#else
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/* Do nothing on other platforms for now.
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*/
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printf( "Not testing OS support for SSE, leaving disabled.\n" );
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gCpuCaps.hasSSE=0;
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#endif /* __linux__ */
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}
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#else /* ARCH_X86 */
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void GetCpuCaps( CpuCaps *caps)
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{
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caps->cpuType=0;
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caps->cpuStepping=0;
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caps->hasMMX=0;
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caps->hasMMX2=0;
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caps->has3DNow=0;
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caps->has3DNowExt=0;
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caps->hasSSE=0;
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caps->hasSSE2=0;
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caps->isX86=0;
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}
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#endif /* !ARCH_X86 */
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