mirror of
https://github.com/mpv-player/mpv
synced 2024-12-21 06:14:32 +00:00
23fb86c8d8
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@24992 b3059339-0415-0410-9bf9-f77b7e298cf2
345 lines
10 KiB
C
345 lines
10 KiB
C
/* small utility to extract CPU information
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Used by configure to set CPU optimization levels on some operating
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systems where /proc/cpuinfo is non-existent or unreliable. */
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#include <stdio.h>
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#include <sys/time.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#if defined(__MINGW32__) && (__MINGW32_MAJOR_VERSION <= 3) && (__MINGW32_MINOR_VERSION < 10)
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#include <sys/timeb.h>
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void gettimeofday(struct timeval* t,void* timezone) {
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struct timeb timebuffer;
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ftime( &timebuffer );
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t->tv_sec=timebuffer.time;
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t->tv_usec=1000*timebuffer.millitm;
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}
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#endif
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#ifdef __MINGW32__
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#define MISSING_USLEEP
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#include <windows.h>
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#define sleep(t) Sleep(1000*t);
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#endif
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#ifdef __BEOS__
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#define usleep(t) snooze(t)
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#endif
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#ifdef M_UNIX
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typedef long long int64_t;
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#define MISSING_USLEEP
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#else
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#include <inttypes.h>
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#endif
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#define CPUID_FEATURE_DEF(bit, desc, description) \
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{ bit, desc }
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typedef struct cpuid_regs {
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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} cpuid_regs_t;
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static cpuid_regs_t
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cpuid(int func) {
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cpuid_regs_t regs;
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#define CPUID ".byte 0x0f, 0xa2; "
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#ifdef __x86_64__
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asm("mov %%rbx, %%rsi\n\t"
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#else
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asm("mov %%ebx, %%esi\n\t"
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#endif
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CPUID"\n\t"
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#ifdef __x86_64__
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"xchg %%rsi, %%rbx\n\t"
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#else
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"xchg %%esi, %%ebx\n\t"
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#endif
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: "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
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: "0" (func));
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return regs;
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}
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static int64_t
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rdtsc(void)
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{
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uint64_t i;
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#define RDTSC ".byte 0x0f, 0x31; "
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asm volatile (RDTSC : "=A"(i) : );
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return i;
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}
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static const char*
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brandname(int i)
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{
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const static char* brandmap[] = {
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NULL,
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"Intel(R) Celeron(R) processor",
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"Intel(R) Pentium(R) III processor",
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"Intel(R) Pentium(R) III Xeon(tm) processor",
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"Intel(R) Pentium(R) III processor",
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NULL,
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"Mobile Intel(R) Pentium(R) III processor-M",
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"Mobile Intel(R) Celeron(R) processor"
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};
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if (i >= sizeof(brandmap))
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return NULL;
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else
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return brandmap[i];
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}
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static void
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store32(char *d, unsigned int v)
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{
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d[0] = v & 0xff;
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d[1] = (v >> 8) & 0xff;
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d[2] = (v >> 16) & 0xff;
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d[3] = (v >> 24) & 0xff;
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}
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int
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main(int argc, char **argv)
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{
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cpuid_regs_t regs, regs_ext;
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char idstr[13];
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unsigned max_cpuid;
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unsigned max_ext_cpuid;
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unsigned int amd_flags;
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unsigned int amd_flags2;
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const char *model_name = NULL;
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int i;
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char processor_name[49];
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regs = cpuid(0);
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max_cpuid = regs.eax;
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/* printf("%d CPUID function codes\n", max_cpuid+1); */
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store32(idstr+0, regs.ebx);
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store32(idstr+4, regs.edx);
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store32(idstr+8, regs.ecx);
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idstr[12] = 0;
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printf("vendor_id\t: %s\n", idstr);
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regs_ext = cpuid((1<<31) + 0);
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max_ext_cpuid = regs_ext.eax;
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if (max_ext_cpuid >= (1<<31) + 1) {
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regs_ext = cpuid((1<<31) + 1);
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amd_flags = regs_ext.edx;
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amd_flags2 = regs_ext.ecx;
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if (max_ext_cpuid >= (1<<31) + 4) {
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for (i = 2; i <= 4; i++) {
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regs_ext = cpuid((1<<31) + i);
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store32(processor_name + (i-2)*16, regs_ext.eax);
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store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
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store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
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store32(processor_name + (i-2)*16 + 12, regs_ext.edx);
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}
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processor_name[48] = 0;
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model_name = processor_name;
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while (*model_name == ' ') {
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model_name++;
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}
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}
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} else {
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amd_flags = 0;
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amd_flags2 = 0;
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}
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if (max_cpuid >= 1) {
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static struct {
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int bit;
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char *desc;
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} cap[] = {
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CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"),
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CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"),
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CPUID_FEATURE_DEF(2, "de", "Debugging Extension"),
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CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"),
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CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"),
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CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"),
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CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"),
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CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"),
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CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"),
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CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"),
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CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"),
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CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"),
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CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"),
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CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"),
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CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"),
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CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"),
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CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"),
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CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"),
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CPUID_FEATURE_DEF(19, "clflush", "CFLUSH instruction"),
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CPUID_FEATURE_DEF(21, "dts", "Debug Store"),
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CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"),
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CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"),
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CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"),
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CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"),
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CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"),
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CPUID_FEATURE_DEF(27, "ss", "Self Snoop"),
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CPUID_FEATURE_DEF(28, "ht", "Multi-threading"),
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CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"),
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CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"),
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CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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} cap2[] = {
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CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"),
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CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"),
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CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"),
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CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"),
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CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"),
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CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"),
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CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
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CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
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CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
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CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
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CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"),
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CPUID_FEATURE_DEF(15, "pdcm", "Perf/Debug Capability MSR"),
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CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"),
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CPUID_FEATURE_DEF(19, "sse4_1", "SSE4.1 Extensions"),
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CPUID_FEATURE_DEF(20, "sse4_2", "SSE4.2 Extensions"),
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CPUID_FEATURE_DEF(23, "popcnt", "Pop Count Instruction"),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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} cap_amd[] = {
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CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
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CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
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CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
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CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
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CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
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CPUID_FEATURE_DEF(26, "pdpe1gb", "PDP Entry for 1GiB Page"),
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CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
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CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
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CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
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CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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} cap_amd2[] = {
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CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
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CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
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CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
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CPUID_FEATURE_DEF(3, "extapic", "Extended APIC Space"),
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CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"),
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CPUID_FEATURE_DEF(5, "abm", "Advanced Bit Manipulation"),
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CPUID_FEATURE_DEF(6, "sse4a", "SSE4A Extensions"),
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CPUID_FEATURE_DEF(7, "misalignsse", "Misaligned SSE Mode"),
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CPUID_FEATURE_DEF(8, "3dnowprefetch", "3DNow! Prefetch/PrefetchW"),
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CPUID_FEATURE_DEF(9, "osvw", "OS Visible Workaround"),
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CPUID_FEATURE_DEF(10, "ibs", "Instruction Based Sampling"),
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CPUID_FEATURE_DEF(11, "sse5", "SSE5 Extensions"),
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CPUID_FEATURE_DEF(12, "skinit", "SKINIT, STGI, and DEV Support"),
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CPUID_FEATURE_DEF(13, "wdt", "Watchdog Timer Support"),
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{ -1 }
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};
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unsigned int family, model, stepping;
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regs = cpuid(1);
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family = (regs.eax >> 8) & 0xf;
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model = (regs.eax >> 4) & 0xf;
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stepping = regs.eax & 0xf;
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if (family == 0xf)
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family += (regs.eax >> 20) & 0xff;
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if (family == 0xf || family == 6)
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model += ((regs.eax >> 16) & 0xf) << 4;
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printf("cpu family\t: %d\n"
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"model\t\t: %d\n"
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"stepping\t: %d\n" ,
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family,
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model,
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stepping);
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if (strstr(idstr, "Intel") && !model_name) {
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if (family == 6 && model == 0xb && stepping == 1)
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model_name = "Intel (R) Celeron (R) processor";
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else
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model_name = brandname(regs.ebx & 0xf);
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}
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printf("flags\t\t:");
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for (i = 0; cap[i].bit >= 0; i++) {
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if (regs.edx & (1 << cap[i].bit)) {
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printf(" %s", cap[i].desc);
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}
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}
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for (i = 0; cap2[i].bit >= 0; i++) {
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if (regs.ecx & (1 << cap2[i].bit)) {
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printf(" %s", cap2[i].desc);
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}
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}
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/* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
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it is not indicated by a CPUID feature bit, so we
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have to check the family, model and stepping instead. */
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if (strstr(idstr, "AMD") &&
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family == 5 &&
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(model >= 9 || model == 8 && stepping >= 8))
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printf(" %s", "k6_mtrr");
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/* similar for cyrix_arr. */
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if (strstr(idstr, "Cyrix") &&
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(family == 5 && model < 4 || family == 6))
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printf(" %s", "cyrix_arr");
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/* as well as centaur_mcr. */
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if (strstr(idstr, "Centaur") &&
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family == 5)
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printf(" %s", "centaur_mcr");
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for (i = 0; cap_amd[i].bit >= 0; i++) {
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if (amd_flags & (1 << cap_amd[i].bit)) {
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printf(" %s", cap_amd[i].desc);
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}
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}
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for (i = 0; cap_amd2[i].bit >= 0; i++) {
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if (amd_flags2 & (1 << cap_amd2[i].bit)) {
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printf(" %s", cap_amd2[i].desc);
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}
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}
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printf("\n");
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if (regs.edx & (1 << 4)) {
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int64_t tsc_start, tsc_end;
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struct timeval tv_start, tv_end;
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int usec_delay;
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tsc_start = rdtsc();
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gettimeofday(&tv_start, NULL);
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#ifdef MISSING_USLEEP
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sleep(1);
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#else
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usleep(100000);
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#endif
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tsc_end = rdtsc();
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gettimeofday(&tv_end, NULL);
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usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec)
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+ (tv_end.tv_usec - tv_start.tv_usec);
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printf("cpu MHz\t\t: %.3f\n",
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(double)(tsc_end-tsc_start) / usec_delay);
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}
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}
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printf("model name\t: ");
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if (model_name)
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printf("%s\n", model_name);
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else
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printf("Unknown %s CPU\n", idstr);
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}
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