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https://github.com/mpv-player/mpv
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New optimized SSE code, overall optimizations.
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@582 b3059339-0415-0410-9bf9-f77b7e298cf2
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atmosfear
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@ -1,12 +1,46 @@
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#ifndef __MPLAYER_MEMCPY
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#define __MPLAYER_MEMCPY
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/*
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This part of code was taken by from Linux-2.4.3 and slightly modified
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for MMX2 instruction set. I have done it since linux uses page aligned
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for MMX2, SSE instruction set. I have done it since linux uses page aligned
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blocks but mplayer uses weakly ordered data and original sources can not
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speedup their. Only using prefetchnta and movntq together have effect!
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speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
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From IA-32 Intel Architecture Software Developer's Manual Volume 1,
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Order Number 245470:
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"10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
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Data referenced by a program can be temporal (data will be used again) or
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non-temporal (data will be referenced once and not reused in the immediate
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future). To make efficient use of the processor's caches, it is generally
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desirable to cache temporal data and not cache non-temporal data. Overloading
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the processor's caches with non-temporal data is sometimes referred to as
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"polluting the caches".
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The non-temporal data is written to memory with Write-Combining semantics.
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The PREFETCHh instructions permits a program to load data into the processor
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at a suggested cache level, so that it is closer to the processors load and
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store unit when it is needed. If the data is already present in a level of
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the cache hierarchy that is closer to the processor, the PREFETCHh instruction
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will not result in any data movement.
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But we should you PREFETCHNTA: Non-temporal data fetch data into location
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close to the processor, minimizing cache pollution.
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The MOVNTQ (store quadword using non-temporal hint) instruction stores
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packed integer data from an MMX register to memory, using a non-temporal hint.
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The MOVNTPS (store packed single-precision floating-point values using
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non-temporal hint) instruction stores packed floating-point data from an
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XMM register to memory, using a non-temporal hint.
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The SFENCE (Store Fence) instruction controls write ordering by creating a
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fence for memory store operations. This instruction guarantees that the results
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of every store instruction that precedes the store fence in program order is
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globally visible before any store instruction that follows the fence. The
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SFENCE instruction provides an efficient way of ensuring ordering between
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procedures that produce weakly-ordered data and procedures that consume that
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data.
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If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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*/
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@ -15,6 +49,11 @@ If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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#if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW )
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#undef HAVE_K6_2PLUS
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#if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
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#define HAVE_K6_2PLUS
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#endif
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/* for small memory blocks (<256 bytes) this version is faster */
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#define small_memcpy(to,from,n)\
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{\
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@ -29,12 +68,11 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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void *p;
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int i;
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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// printf("fastmemcpy_pre(0x%X,0x%X,0x%X)\n",to,from,len);
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// Align dest to 16-byte boundary:
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if((unsigned int)to&15){
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int len2=16-((unsigned int)to&15);
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if((unsigned long)to&15){
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int len2=16-((unsigned long)to&15);
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if(len>len2){
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len-=len2;
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__asm__ __volatile__(
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@ -46,7 +84,6 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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}
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// printf("fastmemcpy(0x%X,0x%X,0x%X)\n",to,from,len);
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#endif
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if(len >= 0x200) /* 512-byte blocks */
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{
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@ -55,13 +92,13 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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len&=63;
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__asm__ __volatile__ (
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#if defined( HAVE_3DNOW ) && !defined( HAVE_MMX2 )
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#ifdef HAVE_K6_2PLUS
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"prefetch (%0)\n"
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"prefetch 64(%0)\n"
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"prefetch 128(%0)\n"
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"prefetch 192(%0)\n"
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"prefetch 256(%0)\n"
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#else
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#else /* K7, P3, CyrixIII */
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"prefetchnta (%0)\n"
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"prefetchnta 64(%0)\n"
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"prefetchnta 128(%0)\n"
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@ -78,15 +115,13 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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perform reading and writing to be multiple to a number of
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processor's decoders, but it's not always possible.
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*/
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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if(((unsigned long)from) & 15)
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/* if SRC is misaligned */
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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#if defined( HAVE_3DNOW ) && !defined( HAVE_MMX2 )
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"prefetch 320(%0)\n"
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#else
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"prefetchnta 320(%0)\n"
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#endif
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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"movups (%0), %%xmm0\n"
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"movups 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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@ -95,8 +130,42 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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"movups 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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#else /* Only K7 (may be other) */
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#if defined( HAVE_3DNOW ) && !defined( HAVE_MMX2 )
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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else
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/*
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Only if SRC is aligned on 16-byte boundary.
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It allows to use movaps instead of movups, which required data
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to be aligned or a general-protection exception (#GP) is generated.
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*/
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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"prefetchnta 320(%0)\n"
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"movaps (%0), %%xmm0\n"
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"movaps 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movaps 32(%0), %%xmm0\n"
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"movaps 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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#else
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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#ifdef HAVE_K6_2PLUS
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"prefetch 320(%0)\n"
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#else
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"prefetchnta 320(%0)\n"
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#endif
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#ifdef HAVE_K6_2PLUS
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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@ -113,7 +182,7 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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"movq %%mm1, 40(%1)\n"
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"movq %%mm2, 48(%1)\n"
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"movq %%mm3, 56(%1)\n"
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#else
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#else /* K7 */
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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@ -130,16 +199,24 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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"movntq %%mm1, 40(%1)\n"
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"movntq %%mm2, 48(%1)\n"
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"movntq %%mm3, 56(%1)\n"
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#endif
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#endif
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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#if defined( HAVE_3DNOW ) && !defined( HAVE_MMX2 )
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#endif /* Have SSE */
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#ifdef HAVE_K6_2PLUS
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/* On K6 femms is fatser of emms.
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On K7 femms is directly mapped on emms. */
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__asm__ __volatile__ ("femms":::"memory");
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#else
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#else /* K7, P3, CyrixIII */
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/* since movntq is weakly-ordered, a "sfence"
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* is needed to become ordered again. */
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__asm__ __volatile__ ("sfence":::"memory");
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#ifndef HAVE_SSE
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/* enables to use FPU */
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__asm__ __volatile__ ("emms":::"memory");
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#endif
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#endif
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}
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/*
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@ -149,7 +226,6 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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return p;
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}
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#define memcpy(a,b,c) fast_memcpy(a,b,c)
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#undef small_memcpy
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#endif
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