mirror of
https://github.com/mpv-player/mpv
synced 2025-02-05 14:42:24 +00:00
YVU9,IF09,Y800 and Y8 support - and synced with mpxp
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@6484 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
alex
parent
63e90b6d98
commit
fd68aff8f7
@ -939,8 +939,14 @@ int vixGetCapability(vidix_capability_t *to)
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return 0;
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}
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/*
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Full list of fourcc which are supported by Win2K redeon driver:
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YUY2, UYVY, DDES, OGLT, OGl2, OGLS, OGLB, OGNT, OGNZ, OGNS,
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IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5
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*/
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uint32_t supported_fourcc[] =
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{
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IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09,
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IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV,
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IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU,
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IMGFMT_RGB15, IMGFMT_BGR15,
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@ -948,9 +954,9 @@ uint32_t supported_fourcc[] =
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IMGFMT_RGB32, IMGFMT_BGR32
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};
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__inline__ static int is_supported_fourcc(uint32_t fourcc)
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inline static int is_supported_fourcc(uint32_t fourcc)
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{
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unsigned i;
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unsigned int i;
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for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++)
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{
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if(fourcc==supported_fourcc[i]) return 1;
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@ -1080,14 +1086,16 @@ static void radeon_vid_display_video( void )
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*/
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case IMGFMT_RGB32:
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case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
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/* 4:1:0*/
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/* 4:1:0 */
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case IMGFMT_IF09:
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case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break;
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/* 4:0:0 */
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case IMGFMT_Y800:
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case IMGFMT_Y8:
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/* 4:2:0 */
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case IMGFMT_IYUV:
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case IMGFMT_I420:
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case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12;
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break;
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case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break;
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/* 4:2:2 */
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case IMGFMT_YVYU:
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case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break;
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@ -1140,6 +1148,8 @@ static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
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if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
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else pitch = 32;
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break;
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/* 4:1:0 */
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case IMGFMT_IF09:
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case IMGFMT_YVU9:
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if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy;
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else pitch = 64;
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@ -1155,16 +1165,20 @@ static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch)
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static int radeon_vid_init_video( vidix_playback_t *config )
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{
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uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top;
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int is_420,is_rgb32,is_rgb,best_pitch,mpitch;
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int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch;
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radeon_vid_stop_video();
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left = config->src.x << 16;
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top = config->src.y << 16;
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src_h = config->src.h;
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src_w = config->src.w;
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is_420 = is_rgb32 = is_rgb = 0;
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is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0;
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if(config->fourcc == IMGFMT_YV12 ||
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config->fourcc == IMGFMT_I420 ||
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config->fourcc == IMGFMT_IYUV) is_420 = 1;
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if(config->fourcc == IMGFMT_YVU9 ||
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config->fourcc == IMGFMT_IF09) is_410 = 1;
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if(config->fourcc == IMGFMT_Y800 ||
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config->fourcc == IMGFMT_Y8) is_400 = 1;
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if(config->fourcc == IMGFMT_RGB32 ||
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config->fourcc == IMGFMT_BGR32) is_rgb32 = 1;
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if(config->fourcc == IMGFMT_RGB32 ||
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@ -1179,7 +1193,12 @@ static int radeon_vid_init_video( vidix_playback_t *config )
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mpitch = best_pitch-1;
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switch(config->fourcc)
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{
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/* 4:0:0 */
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case IMGFMT_Y800:
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case IMGFMT_Y8:
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/* 4:1:0 */
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case IMGFMT_YVU9:
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case IMGFMT_IF09:
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/* 4:2:0 */
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case IMGFMT_IYUV:
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case IMGFMT_YV12:
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@ -1222,27 +1241,74 @@ static int radeon_vid_init_video( vidix_playback_t *config )
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config->offsets[0] = 0;
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for(i=1;i<besr.vid_nbufs;i++)
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config->offsets[i] = config->offsets[i-1]+config->frame_size;
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if(is_420)
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if(is_420 || is_410 || is_400)
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{
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uint32_t d1line,d2line,d3line;
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d1line = top*pitch;
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d2line = src_h*pitch+(d1line>>2);
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d3line = d2line+((src_h*pitch)>>2);
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if(is_420)
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{
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d2line = src_h*pitch+(d1line>>2);
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d3line = d2line+((src_h*pitch)>>2);
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}
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else
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if(is_410)
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{
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d2line = src_h*pitch+(d1line>>4);
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d3line = d2line+((src_h*pitch)>>4);
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}
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else
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{
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d2line = 0;
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d3line = 0;
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}
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d1line += (left >> 16) & ~15;
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d2line += (left >> 17) & ~15;
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d3line += (left >> 17) & ~15;
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if(is_420)
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{
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d2line += (left >> 17) & ~15;
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d3line += (left >> 17) & ~15;
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}
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else
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if(is_410)
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{
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d2line += (left >> 18) & ~15;
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d3line += (left >> 18) & ~15;
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}
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config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK;
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config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK;
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config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK;
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if(is_400)
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{
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config->offset.v = 0;
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config->offset.u = 0;
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}
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else
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{
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config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK;
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config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK;
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}
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for(i=0;i<besr.vid_nbufs;i++)
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{
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besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK);
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besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
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besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
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if(is_400)
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{
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besr.vid_buf_base_adrs_v[i]=0;
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besr.vid_buf_base_adrs_u[i]=0;
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}
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else
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{
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besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
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besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
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}
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}
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config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off;
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config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
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config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
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if(is_400)
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{
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config->offset.v = 0;
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config->offset.u = 0;
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}
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else
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{
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config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
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config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
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}
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if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
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{
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uint32_t tmp;
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@ -1274,33 +1340,44 @@ static int radeon_vid_init_video( vidix_playback_t *config )
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|(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);
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tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
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besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK)
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besr.p23_v_accum_init = (is_420||is_410) ?
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((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK)
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|(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0;
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leftUV = (left >> 17) & 15;
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leftUV = (left >> (is_410?18:17)) & 15;
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left = (left >> 16) & 15;
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if(is_rgb && !is_rgb32) h_inc<<=1;
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if(is_rgb32)
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besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16);
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else
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if(is_410)
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besr.h_inc = h_inc | ((h_inc >> 2) << 16);
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else
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besr.h_inc = h_inc | ((h_inc >> 1) << 16);
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besr.step_by = step_by | (step_by << 8);
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besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16);
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besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16);
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besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
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if(is_420)
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if(is_420 || is_410)
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{
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src_h = (src_h + 1) >> 1;
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src_h = (src_h + 1) >> (is_410?2:1);
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besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
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}
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else besr.p23_blank_lines_at_top = 0;
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besr.vid_buf_pitch0_value = pitch;
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besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch;
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besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch;
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besr.p1_x_start_end = (src_w+left-1)|(left<<16);
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src_w>>=1;
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besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
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besr.p3_x_start_end = besr.p2_x_start_end;
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if (is_410||is_420) src_w>>=is_410?2:1;
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if(is_400)
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{
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besr.p2_x_start_end = 0;
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besr.p3_x_start_end = 0;
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}
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else
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{
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besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
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besr.p3_x_start_end = besr.p2_x_start_end;
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}
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return 0;
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}
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@ -1318,6 +1395,16 @@ static void radeon_compute_framesize(vidix_playback_t *info)
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awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
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info->frame_size = awidth*(info->src.h+info->src.h/2);
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break;
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case IMGFMT_Y800:
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case IMGFMT_Y8:
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awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
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info->frame_size = awidth*info->src.h;
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break;
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case IMGFMT_IF09:
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case IMGFMT_YVU9:
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awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
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info->frame_size = awidth*(info->src.h+info->src.h/8);
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break;
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case IMGFMT_RGB32:
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case IMGFMT_BGR32:
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awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
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