mirror of
https://github.com/mpv-player/mpv
synced 2025-01-02 21:12:23 +00:00
Changed code, should be faster on Athlon/K6 but slower on PIII with SSE, more portable.
git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@645 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
atmosfear
parent
4fa0ab76e6
commit
fc6fab0429
@ -1,13 +1,17 @@
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#ifndef __MPLAYER_MEMCPY
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#define __MPLAYER_MEMCPY
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#define __MPLAYER_MEMCPY 1
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#ifdef USE_FASTMEMCPY
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#include <stddef.h>
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/*
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This part of code was taken by from Linux-2.4.3 and slightly modified
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for MMX2, SSE instruction set. I have done it since linux uses page aligned
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for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
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blocks but mplayer uses weakly ordered data and original sources can not
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speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
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From IA-32 Intel Architecture Software Developer's Manual Volume 1,
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>From IA-32 Intel Architecture Software Developer's Manual Volume 1,
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Order Number 245470:
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"10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
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@ -16,7 +20,7 @@ non-temporal (data will be referenced once and not reused in the immediate
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future). To make efficient use of the processor's caches, it is generally
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desirable to cache temporal data and not cache non-temporal data. Overloading
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the processor's caches with non-temporal data is sometimes referred to as
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"polluting the caches".
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"polluting the caches".
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The non-temporal data is written to memory with Write-Combining semantics.
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The PREFETCHh instructions permits a program to load data into the processor
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@ -47,7 +51,18 @@ If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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// 3dnow memcpy support from kernel 2.4.2
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// by Pontscho/fresh!mindworkz
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#if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW )
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#if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX )
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#undef HAVE_MMX1
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#if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
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/* means: mmx v.1. Note: Since we added alignment of destinition it speedups
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of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
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standard (non MMX-optimized) version.
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Note: on K6-2+ it speedups memory copying upto 25% and
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on K7 and P3 about 500% (5 times). */
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#define HAVE_MMX1
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#endif
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#undef HAVE_K6_2PLUS
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#if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
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@ -58,54 +73,65 @@ If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
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#define small_memcpy(to,from,n)\
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{\
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__asm__ __volatile__(\
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"rep ; movsb\n"\
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::"D" (to), "S" (from),"c" (n)\
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: "memory");\
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"rep; movsb"\
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:"=D"(to), "=S"(from), "=c"(n)\
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/* It's most portable way to notify compiler */\
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/* that edi, esi and ecx are clobbered in asm block. */\
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/* Thanks to A'rpi for hint!!! */\
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:"0" (to), "1" (from),"2" (n)\
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: "memory");\
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}
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inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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{
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void *p;
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int i;
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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// printf("fastmemcpy_pre(0x%X,0x%X,0x%X)\n",to,from,len);
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// Align dest to 16-byte boundary:
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if((unsigned long)to&15){
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int len2=16-((unsigned long)to&15);
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if(len>len2){
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len-=len2;
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__asm__ __volatile__(
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"rep ; movsb\n"
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:"=D" (to), "=S" (from)
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: "D" (to), "S" (from),"c" (len2)
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: "memory");
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}
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}
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// printf("fastmemcpy(0x%X,0x%X,0x%X)\n",to,from,len);
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#ifdef HAVE_SSE
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#define MMREG_SIZE 16
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#else
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#define MMREG_SIZE 8
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#endif
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if(len >= 0x200) /* 512-byte blocks */
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{
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p = to;
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i = len >> 6; /* len/64 */
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len&=63;
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__asm__ __volatile__ (
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/* Small defines (for readability only) ;) */
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#ifdef HAVE_K6_2PLUS
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"prefetch (%0)\n"
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"prefetch 64(%0)\n"
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"prefetch 128(%0)\n"
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"prefetch 192(%0)\n"
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"prefetch 256(%0)\n"
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#else /* K7, P3, CyrixIII */
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"prefetchnta (%0)\n"
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"prefetchnta 64(%0)\n"
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"prefetchnta 128(%0)\n"
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"prefetchnta 192(%0)\n"
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"prefetchnta 256(%0)\n"
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#define PREFETCH "prefetch"
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/* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
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#define EMMS "femms"
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#else
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#define PREFETCH "prefetchnta"
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#define EMMS "emms"
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#endif
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#ifdef HAVE_MMX2
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#define MOVNTQ "movntq"
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#else
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#define MOVNTQ "movq"
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#endif
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inline static void * fast_memcpy(void * to, const void * from, size_t len)
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{
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void *retval;
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int i;
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retval = to;
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if(len >= 0x200) /* 512-byte blocks */
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{
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register unsigned long int delta;
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/* Align destinition to MMREG_SIZE -boundary */
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delta = ((unsigned long int)to)&(MMREG_SIZE-1);
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if(delta)
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{
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delta=MMREG_SIZE-delta;
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len -= delta;
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small_memcpy(to, from, delta);
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}
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i = len >> 6; /* len/64 */
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len&=63;
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#ifndef HAVE_MMX1
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__asm__ __volatile__ (
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PREFETCH" (%0)\n"
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PREFETCH" 64(%0)\n"
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PREFETCH" 128(%0)\n"
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PREFETCH" 192(%0)\n"
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PREFETCH" 256(%0)\n"
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: : "r" (from) );
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#endif
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: : "r" (from) );
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/*
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This algorithm is top effective when the code consequently
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reads and writes blocks which have size of cache line.
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@ -116,114 +142,89 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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processor's decoders, but it's not always possible.
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*/
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#ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
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if(((unsigned long)from) & 15)
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/* if SRC is misaligned */
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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"prefetchnta 320(%0)\n"
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"movups (%0), %%xmm0\n"
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"movups 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movups 32(%0), %%xmm0\n"
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"movups 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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else
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/*
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Only if SRC is aligned on 16-byte boundary.
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It allows to use movaps instead of movups, which required data
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to be aligned or a general-protection exception (#GP) is generated.
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*/
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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"prefetchnta 320(%0)\n"
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"movaps (%0), %%xmm0\n"
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"movaps 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movaps 32(%0), %%xmm0\n"
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"movaps 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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if(((unsigned long)from) & 15)
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/* if SRC is misaligned */
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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PREFETCH" 320(%0)\n"
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"movups (%0), %%xmm0\n"
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"movups 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movups 32(%0), %%xmm0\n"
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"movups 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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((const unsigned char *)from)+=64;
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((unsigned char *)to)+=64;
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}
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else
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/*
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Only if SRC is aligned on 16-byte boundary.
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It allows to use movaps instead of movups, which required data
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to be aligned or a general-protection exception (#GP) is generated.
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*/
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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PREFETCH" 320(%0)\n"
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"movaps (%0), %%xmm0\n"
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"movaps 16(%0), %%xmm1\n"
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"movntps %%xmm0, (%1)\n"
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"movntps %%xmm1, 16(%1)\n"
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"movaps 32(%0), %%xmm0\n"
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"movaps 48(%0), %%xmm1\n"
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"movntps %%xmm0, 32(%1)\n"
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"movntps %%xmm1, 48(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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((const unsigned char *)from)+=64;
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((unsigned char *)to)+=64;
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}
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#else
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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#ifdef HAVE_K6_2PLUS
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"prefetch 320(%0)\n"
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#else
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"prefetchnta 320(%0)\n"
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for(; i>0; i--)
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{
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__asm__ __volatile__ (
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#ifndef HAVE_MMX1
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PREFETCH" 320(%0)\n"
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#endif
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#ifdef HAVE_K6_2PLUS
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"movq %%mm0, (%1)\n"
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"movq %%mm1, 8(%1)\n"
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"movq %%mm2, 16(%1)\n"
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"movq %%mm3, 24(%1)\n"
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"movq 32(%0), %%mm0\n"
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"movq 40(%0), %%mm1\n"
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"movq 48(%0), %%mm2\n"
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"movq 56(%0), %%mm3\n"
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"movq %%mm0, 32(%1)\n"
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"movq %%mm1, 40(%1)\n"
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"movq %%mm2, 48(%1)\n"
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"movq %%mm3, 56(%1)\n"
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#else /* K7 */
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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"movntq %%mm0, (%1)\n"
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"movntq %%mm1, 8(%1)\n"
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"movntq %%mm2, 16(%1)\n"
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"movntq %%mm3, 24(%1)\n"
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"movq 32(%0), %%mm0\n"
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"movq 40(%0), %%mm1\n"
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"movq 48(%0), %%mm2\n"
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"movq 56(%0), %%mm3\n"
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"movntq %%mm0, 32(%1)\n"
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"movntq %%mm1, 40(%1)\n"
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"movntq %%mm2, 48(%1)\n"
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"movntq %%mm3, 56(%1)\n"
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#endif
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:: "r" (from), "r" (to) : "memory");
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from+=64;
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to+=64;
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}
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"movq (%0), %%mm0\n"
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"movq 8(%0), %%mm1\n"
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"movq 16(%0), %%mm2\n"
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"movq 24(%0), %%mm3\n"
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MOVNTQ" %%mm0, (%1)\n"
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MOVNTQ" %%mm1, 8(%1)\n"
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MOVNTQ" %%mm2, 16(%1)\n"
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MOVNTQ" %%mm3, 24(%1)\n"
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"movq 32(%0), %%mm0\n"
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"movq 40(%0), %%mm1\n"
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"movq 48(%0), %%mm2\n"
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"movq 56(%0), %%mm3\n"
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MOVNTQ" %%mm0, 32(%1)\n"
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MOVNTQ" %%mm1, 40(%1)\n"
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MOVNTQ" %%mm2, 48(%1)\n"
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MOVNTQ" %%mm3, 56(%1)\n"
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:: "r" (from), "r" (to) : "memory");
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((const unsigned char *)from)+=64;
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((unsigned char *)to)+=64;
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}
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#endif /* Have SSE */
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#ifdef HAVE_K6_2PLUS
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/* On K6 femms is fatser of emms.
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On K7 femms is directly mapped on emms. */
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__asm__ __volatile__ ("femms":::"memory");
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#else /* K7, P3, CyrixIII */
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#ifdef HAVE_MMX2
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/* since movntq is weakly-ordered, a "sfence"
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* is needed to become ordered again. */
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__asm__ __volatile__ ("sfence":::"memory");
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#ifndef HAVE_SSE
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/* enables to use FPU */
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__asm__ __volatile__ ("emms":::"memory");
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#endif
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* is needed to become ordered again. */
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__asm__ __volatile__ ("sfence":::"memory");
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#endif
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}
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/*
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* Now do the tail of the block
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*/
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small_memcpy(to, from, len);
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return p;
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#ifndef HAVE_SSE
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/* enables to use FPU */
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__asm__ __volatile__ (EMMS:::"memory");
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#endif
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}
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/*
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* Now do the tail of the block
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*/
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if(len) small_memcpy(to, from, len);
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return retval;
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}
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#define memcpy(a,b,c) fast_memcpy(a,b,c)
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#undef small_memcpy
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@ -231,3 +232,5 @@ inline static void * fast_memcpy(void * to, const void * from, unsigned len)
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#endif
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#endif
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#endif
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