mirror of https://github.com/mpv-player/mpv
Convert strings to comments since they're never used,
patch by Zuxy Meng % zuxy P meng A gmail P com % Original thread: Date: Sep 19, 2006 7:33 AM Subject: [MPlayer-dev-eng] [PATCH] Cleanup of TOOLS/cpuinfo.c git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@20005 b3059339-0415-0410-9bf9-f77b7e298cf2
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gpoirier
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110
TOOLS/cpuinfo.c
110
TOOLS/cpuinfo.c
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@ -33,6 +33,8 @@ typedef long long int64_t;
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#include <inttypes.h>
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#endif
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#define CPUID_FEATURE_DEF(bit, desc, description) \
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{ bit, desc }
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typedef struct cpuid_regs {
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unsigned int eax;
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@ -151,81 +153,77 @@ main(int argc, char **argv)
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static struct {
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int bit;
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char *desc;;
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char *description;
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} cap[] = {
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{ 0, "fpu", "Floating-point unit on-chip" },
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{ 1, "vme", "Virtual Mode Enhancements" },
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{ 2, "de", "Debugging Extension" },
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{ 3, "pse", "Page Size Extension" },
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{ 4, "tsc", "Time Stamp Counter" },
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{ 5, "msr", "Pentium Processor MSR" },
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{ 6, "pae", "Physical Address Extension" },
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{ 7, "mce", "Machine Check Exception" },
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{ 8, "cx8", "CMPXCHG8B Instruction Supported" },
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{ 9, "apic", "On-chip APIC Hardware Enabled" },
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{ 11, "sep", "SYSENTER and SYSEXIT" },
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{ 12, "mtrr", "Memory Type Range Registers" },
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{ 13, "pge", "PTE Global Bit" },
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{ 14, "mca", "Machine Check Architecture" },
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{ 15, "cmov", "Conditional Move/Compare Instruction" },
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{ 16, "pat", "Page Attribute Table" },
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{ 17, "pse36", "Page Size Extension 36-bit" },
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{ 18, "pn", "Processor Serial Number" },
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{ 19, "cflsh", "CFLUSH instruction" },
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{ 21, "dts", "Debug Store" },
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{ 22, "acpi", "Thermal Monitor and Clock Ctrl" },
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{ 23, "mmx", "MMX Technology" },
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{ 24, "fxsr", "FXSAVE/FXRSTOR" },
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{ 25, "sse", "SSE Extensions" },
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{ 26, "sse2", "SSE2 Extensions" },
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{ 27, "ss", "Self Snoop" },
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{ 28, "ht", "Multi-threading" },
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{ 29, "tm", "Therm. Monitor" },
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{ 30, "ia64", "IA-64 Processor" },
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{ 31, "pbe", "Pend. Brk. EN." },
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CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"),
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CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"),
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CPUID_FEATURE_DEF(2, "de", "Debugging Extension"),
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CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"),
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CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"),
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CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"),
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CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"),
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CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"),
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CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"),
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CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"),
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CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"),
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CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"),
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CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"),
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CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"),
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CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"),
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CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"),
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CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"),
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CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"),
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CPUID_FEATURE_DEF(19, "cflsh", "CFLUSH instruction"),
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CPUID_FEATURE_DEF(21, "dts", "Debug Store"),
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CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"),
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CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"),
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CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"),
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CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"),
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CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"),
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CPUID_FEATURE_DEF(27, "ss", "Self Snoop"),
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CPUID_FEATURE_DEF(28, "ht", "Multi-threading"),
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CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"),
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CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"),
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CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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char *description;
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} cap2[] = {
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{ 0, "pni", "SSE3 Extensions" },
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{ 3, "monitor", "MONITOR/MWAIT" },
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{ 4, "ds_cpl", "CPL Qualified Debug Store" },
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{ 5, "vmx", "Virtual Machine Extensions" },
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{ 7, "est", "Enhanced Intel SpeedStep Technology" },
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{ 8, "tm2", "Thermal Monitor 2" },
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{ 10, "cid", "L1 Context ID" },
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{ 13, "cx16", "CMPXCHG16B Available" },
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{ 14, "xtpr", "xTPR Disable" },
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CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"),
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CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"),
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CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"),
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CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"),
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CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"),
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CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
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CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
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CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
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CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;;
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char *description;
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} cap_amd[] = {
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{ 11, "syscall", "SYSCALL and SYSRET" },
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{ 19, "mp", "MP Capable" },
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{ 20, "nx", "No-Execute Page Protection" },
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{ 22, "mmxext","MMX Technology (AMD Extensions)" },
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{ 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" },
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{ 27, "rdtscp", "RDTSCP Instruction" },
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{ 29, "lm", "Long Mode Capable" },
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{ 30, "3dnowext","3DNow! Extensions" },
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{ 31, "3dnow", "3DNow!" },
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CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
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CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
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CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
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CPUID_FEATURE_DEF(22, "mmxext","MMX Technology (AMD Extensions)"),
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CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
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CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
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CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
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CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
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CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
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{ -1 }
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};
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static struct {
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int bit;
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char *desc;
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char *description;
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} cap_amd2[] = {
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{ 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" },
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{ 1, "cmp_legacy", "Chip Multi-Core" },
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{ 2, "svm", "Secure Virtual Machine" },
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{ 4, "cr8legacy", "CR8 Available in Legacy Mode" },
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CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
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CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
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CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
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CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"),
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{ -1 }
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};
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unsigned int family, model, stepping;
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