Fixing "quake" by direct waiting of vsync.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(I don't why - but SMART_SWITCH is always disabled on my card)
Benchmarks:
[SRC] VIDEO:  [DIV3]  624x356  24bpp  24.00 fps  497.3 kbps (60.7 kbyte/s)
[DEST] 1024x768@32 70fps (-xvidix -fs -zoom)

-vc ffdivx -double:
BENCHMARKs: V:   3.838s VO:   7.305s A:   0.555s Sys:  18.264s =   29.962s
BENCHMARK%: V: 12.8110% VO: 24.3808% A:  1.8518% Sys: 60.9564% = 100.0000%
total video time: 11.143s

-vc ffdivx -nodouble:
BENCHMARKs: V:   3.846s VO:   1.668s A:   0.539s Sys:  23.869s =   29.922s
BENCHMARK%: V: 12.8525% VO:  5.5744% A:  1.8015% Sys: 79.7716% = 100.0000%
total video time: 5.514s

-vc divxds -double (direct rendering)
BENCHMARKs: V:   8.275s VO:   5.750s A:   0.532s Sys:  15.414s =   29.971s
BENCHMARK%: V: 27.6115% VO: 19.1850% A:  1.7737% Sys: 51.4298% = 100.0000%
total video time: 14.070s

-vc divxds -nodouble (direct rendering)
BENCHMARKs: V:   7.353s VO:   0.002s A:   0.521s Sys:  22.083s =   29.958s
BENCHMARK%: V: 24.5433% VO:  0.0052% A:  1.7382% Sys: 73.7133% = 100.0000%
total video time: 7.355s

Unfortunately we have dramatic lost of performance (100%) :(


git-svn-id: svn://svn.mplayerhq.hu/mplayer/trunk@4690 b3059339-0415-0410-9bf9-f77b7e298cf2
This commit is contained in:
nick 2002-02-13 08:24:13 +00:00
parent 783fe75c9c
commit ee56ddac74
1 changed files with 15 additions and 0 deletions

View File

@ -270,6 +270,18 @@ static uint32_t radeon_get_yres( void )
return yres + 1;
}
static void radeon_wait_vsync(void)
{
int i;
OUTREG(GEN_INT_STATUS, VSYNC_INT_AK);
for (i = 0; i < 2000000; i++)
{
if (INREG(GEN_INT_STATUS) & VSYNC_INT) break;
}
}
static __inline__ void radeon_engine_flush ( void )
{
int i;
@ -919,6 +931,8 @@ static void radeon_vid_display_video( void )
OUTREG(FCP_CNTL, FCP_CNTL__GND);
OUTREG(CAP0_TRIG_CNTL, 0);
OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01);
OUTREG(DISP_TEST_DEBUG_CNTL, 0);
OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
@ -1292,6 +1306,7 @@ int vixPlaybackFrameSelect(unsigned frame)
off[4] = besr.vid_buf4_base_adrs;
off[5] = besr.vid_buf5_base_adrs;
}
radeon_wait_vsync();
radeon_fifo_wait(2);
OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
radeon_engine_idle();